Omap-L138 McBSP CLKR/CLKX

The skew between CLKR and CLKX is not specified because CLKX is used for the transmit channel along with DX and FSX  while CLKR is for the receive channel along with DR and FSR.  On the OMAP35x devices the McBSP can be switched to 4-pin mode and use CLKX and FSX for both transmit and receive.

  Paul

Hello Paul.

Thank you for your respond.

I understand that CLKX and CLKR are design to be used separately for TX and RX channels.

But in case when the receive (RX) channel only is required and TX channel is not used - CLKX can provide the option to have inverted CLKX when CLKR is not inverted since they are controlled separately. So we can have CLKR (on CLKR pin) and CLKR_inverted (on CLKX_pin).

That requires the skew between CLKX and CLKR to be small.

And technically the skew must be very small - the both CLKX and CLKR have the same source - CLKG and routed to the output pins through the same type of muxes.

And output pins are very close.

It would be very useful to have this parameter (skew between CLKX and CLKR) in Omap-L138 data sheet.

Boris Ruvinsky

What would the CLKR_inverted (CLKX pin) used for?

  Paul

Paul,

In some designs - it is necessary to have serial data "re-clocked" using different CLK edges. The simple discrete inverter can introduce significant delay.

So the option to have CLK and CLK_inverted is very useful in some cases.

And ths would cost nothing when McBSP is used for RX only.

Thank you,  Boris

Boris

I know that this is not a parameter we characterize for the OMAP35x devices and this probably also true for the OMAPL-1 devices since your use of the clocks  is not a standard operating mode. 

Can you tell me more about the McBSP RX configuration? Is FSR free running (continuous data)? Is the FSX pin available? What's the reason for the re-clock?

  Paul

Paul,

Omap-L138 McBSP is used for communication (read serial data) with ADC ADS1274-ADS1278 (TI devices).

ADS1274-1278:

The ADS1274 CLK = SCLK = (80/3)MHz maximum which gives us 37.5nS period minimum.

FSYNC is free running with tFRAME = 256 * CLK.

The DOUT delay from FSYNC_high = 25nS max (ADS1274 DS-p9)

McBSP:

There two ways (as I see) to configure McBSP:

The first approach:

1.  Configure CLKR and FSR as internal. DR setup to CLKR is 14nS min (Omap-L138 DS-p163). Data Delay is set to 1-bit period (McBSP UG-p24)

2.  Make CLR inverted and connect CLKR to ADS1274 CLK and SCLK. FSR is connected to FSYNC.

3.  DOUT will go to DR on McBSP. DOUT (MSB) delay from SCLK falling edge can be (25 +5.5)=30.5nS - (FSYNC-to-DOUT_del + CLKR-to-FSR_del)

4. That leaves us with 7ns setup for DR to CLKR falling edge min. To make the system work - DOUT from ADS1274 needs to be re-clocked before connected to DR.

5. The DOUT can be re-clocked by SCLK falling edge and then connected to DR. With very fast external D-FF (2-3nS delay) we can get the setup to the next (falling CLKR edge) = 37.5/2 -3 = 15.75nS. This time does not include SCLK inverter delay (D-FF has positive CLK).

6.  The re-clocking can be done in two stages (with Data Delay set to 2-bit period) to eliminate the problem of SCLK inverter delay. But this is getting more complicated when we use the discrete components.

The second approach:

1.  On McBSP use CLKX and FSX to ADS1274 CLK and FSYNC. Make CLKX inverted.

2.  Connect CLKX_pin to CLKR_pin - make CLKR_external and non inverted. CLKR_external repeats CLKX-pin and SCLK. DR setup to CLKR_external = 4nS min (Omap DS-p163).

3.  FSX which is used as FSYNC on ADS1274 and will be connected to FSR_pin and used as FSR_external. But FSX_internal must be re-clocked before connecting to FSR_pin because FSX_internal has uncertain timing to CLKX_internal (-4,5.5) nS. But this re-clocking is easier - CLKX_pin rising edge is used. I would really want to eliminate this re-clocking but looks like it is necessary. What do you think?

4.  The resulting FSR_external and CLKR_extenal allow us to read the data from DR_pin (DOUT from ADS1274) with setup min of (37.5-(25+5.5))=7nS (for MSB). McBSP setup requirement for DR to CKLR_external = 4nS min.

5.  The Data Delay must be set to 0-bit (McBSP UG-p24) since FSX_pin is re-clocked and used as FSR_external.

It looks like the system will work in this configuration. 

Am I missing something?

What is your opinion? Do you know the better way to configure McBSP when is used with ADS1274-1278?

Thank you for your help,

Boris Ruvinsky

Boris

The second approach is basically what I came up with. I've pinged a couple of other engineers to see if they have a better solution.

  Paul