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Original question:

Cache miss for DSP

TDA4VM: ARM PMU

Guoxun
Intellectual 670 points
Part Number: TDA4VM

On TDA4VM, there are two instances of the dual-core Arm Cortex-R5F processor and one dual-core Arm Cortex-A72 Microprocessor Unit (MPU)  integrated in MAIN domain.

So, there are 2 Arm Cortex-A72 and 4 Arm Cortex-R5F integrated in MAIN domain?

Arm Cortex-A72  is as shown.

There are 4 cores for each Arm Cortex-A72.

How many Cortex-A72 cores integrated on TDA4vm in total?  2 or 8(2 processors* 4 cores)?

There is one PMU for each core? or  there is one PMU for all cores?

 If one PMU for all cores, PMU count all cache miss/hit on all cores?

  • 0
    TI__Mastermind 20075 points

    Hello Guoxun,

    TDA4VM has one A72MP cluster which has 2 A72 cores.  Each core has a private PMU unit which counts events from its point of view.  When you use the PMU to do analysis you will consult both PMU instances.  If you are running in an SMP mode with Linux, tools typically symmetrical setup each PMU unit.

    See the below picture for an example on TDA4VM.  This report is generated using the TRACE32 debugger.  Each PMU is set to capture L2 Data refills and CPU cycles.  The numbers in the BMC (benchmark counter) display are of the total events over 5.1seconds.  The graph is a frequency chart which shows the # of events over that same 5.1s.  You can see in this example run that CPU1 is generated a lot more L2 data refills than CPU0.  The core cycle count is different as while in the idle instruction a core is not accumulating cycles.

    This type of report is quite nice but it can be further enhanced if processor trace is also collected.  In a that expanded report (trace + pmu events | across time) it is possible to make out which functions are running during misses.

    The number of cores is a TI TDAVM configuration option.  The PMU information is generic for ARM and more information can be found in the ARM TRMs.

    Regards,

    Richard W.