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AM5746: How to change SBL MMU configuration by the bare metal application

KTM
Intellectual 850 points
Part Number: AM5746


I have a bare metal AM574x application on a custom board that uses the SBL provided by the SDK.  We are booting via QSPI.  The application accesses an external SRAM part via the GPMC.  In addition to the normal MMU configurations, the application configures the MMU to account for the GPMC register and memory spaces.  The application works fine when debugging and using the GEL scripts. 

When we move to using the SBL, how should the application's MMU configuration steps change since cache is already enabled and the MMU configured by the SBL?  That is, do I need to account for the SBL already having configured the MMU?  If so, how? 

Thanks,

KTM

  • 0
    TI__Guru 50045 points

    Hi,

    Please refer to SBL_MMUInit() in ~/pdk_am57xx_1_0_17/packages/ti/boot/sbl/soc/am57xx/sbl_startup.c.

    It maps 0x0 ~ 0x6000_0000 and 0x8000_0000 ~ 0xFFFF_FFFF in MMU.

    That includes GPMC memory space so you can access GPMC from your app without modifying SBL MMU config.

    Regards,
    Stanley

  • 0 in reply to Stanley Liu
    Intellectual 850 points

    Hi,

    I would like to also be able to run the application without the SBL.  Can I simply include the function SBL_MMUInit() in my application and exclude it when using the SBL?  Will the GEL scripts cause any issues with the MMU setup?  Is there a performance hit with so many MMU table entries? 

    The MMU setup in the SBL is relatively simple.  Why are there so many E2E posts talking about adding MMU table entries for individual peripherals? 

    Thanks,

    KTM

  • +1 in reply to KTM
    TI__Guru 50045 points

    Yes. I think you can do that. GEL script doesn't configure A15 MMU.

    I don't think there is performance impact due to MMU.

    The way SBL maps complete 0x0~0x6000_0000 in MMU is not the most efficient way since it covers address space where there is no valid physical memory or registers. Some may choose to only map the address space with memory/registers.

  • 0 in reply to Stanley Liu
    Intellectual 850 points

    Thanks for the information!