• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 97 subscribers
  • Views 1102 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Clocking Options for C6748

DanB57495
Expert 1340 points

Hi Guys,

Background:

I am putting together some schematics for a C6748 that will use mDDR at 132MHz, NOR-flash, 2 UARTS, Ethernet. These portions are similar to the  C6748 SOM design from Logic PD (meaning the same I/O lines and clocking methods will likely be used for these parts). The main internal clock will run at 300MHz. In addition, we will need to use the Universal Parallel Port (UPP) (16-bits) with a DMA running output data at 150kHz to a DAC and we will need to generate 600kHz (externally) to supply an ADC.

Question:

Bearing in mind the constraints above is it possible to generate the 150kHz for the UPP for DMA and provide an output on one of the C6748 outputs that generates 600kHz all internally? Is it possible to direct internal clock output to output pins in general?

I believe the UPP had an option for external clock so I could provide 75kHz for this if needed, but in that case I would then generate these two frequencies externally, and likely provide the C6748 clock from the same source.

Thanks in advance for your help.

Dan.

 

 

 

  • 0
    TI__Genius 14545 points

    Dan,

    DanB said:
    Bearing in mind the constraints above is it possible to generate the 150kHz for the UPP for DMA and provide an output on one of the C6748 outputs that generates 600kHz all internally? Is it possible to direct internal clock output to output pins in general?

    uPP runs off the SYSCLK2  clock zone, which is a /2 of the SYSCLK1 clock zone. You can then further divide this down by the PLLDIV2 clock divider register as well as the clock divider regsiter in the uPP itself, however that's a total /1000.

     

    PLLDIV2 can do a Max /32 so this means that the uPP would have to divide by an additional 31.25 to achieve the 150kHz frequency.  The clock divider for uPP is a /16 max - so it doesn't appear as though you can obtain a 150kHz internal uPP clock by using a 300MHz SYSCLK1. You can verify this in the C6748 System Reference Guide / and uPP User Guide to check and see if I make a mistake.

     

    DanB said:
    I believe the UPP had an option for external clock so I could provide 75kHz for this if needed, but in that case I would then generate these two frequencies externally, and likely provide the C6748 clock from the same source.

    This is correct, you can provide a clock to the uPP externally. See the uPP User Guide for details.

  • 0 in reply to dabuan
    Expert 1340 points

    Hi Drew,

    Thanks for your answer and the references, it looks I will need to use external clocking components  for the system. One question that I haven't yet determined is whether it is possible to direct C6748 internal clocks to General purpose I/O so that components outside of the C6748 IC can make use of these clocks? I say GPIO so that we would not have to sacrifice an output that was originally dedicated for a specific I/O purpose (like SPI).

    One minor additional item that I did not yet find an answer to: If the C6748 is being driven by a clock instead of a crystal (so we are clocking "OSCIN" and leaving "OSCOUT") is there a register setting that needs to change to accomodate this?

    Thanks again.

    Dan.

     

  • 0 in reply to DanB57495
    TI__Genius 14545 points

    Dan,

    DanB said:
    One question that I haven't yet determined is whether it is possible to direct C6748 internal clocks to General purpose I/O so that components outside of the C6748 IC can make use of these clocks?

    At the System Level, there is a mux which lets you output any of the clock domains out to an external pin. Please refer to the Phase Locked Loop Controller (PLLC) in the Device System Reference Guide for a pictoral overview of the clocking structure.

     

    DanB said:
    If the C6748 is being driven by a clock instead of a crystal (so we are clocking "OSCIN" and leaving "OSCOUT") is there a register setting that needs to change to accomodate this?

    Yes - There are instructions on how to configure the PLLC in the System Reference Guide as well. Driving a square wave into the part is not an issue as long as you meet the electrical specifications as specified in the device datasheet.

     

     

  • 0 in reply to dabuan
    Expert 1340 points

    Hi Drew,

     

    Thanks for pointing me in the right direction. I see that the "CLKOUT" pin can be used to output internal clocking and the PLLC0 bit 8 handles input selection.

    Thanks again very much.

     

    Dan.

  • 0
    TI__Genius 17355 points

    DanB said:
    I believe the UPP had an option for external clock so I could provide 75kHz for this if needed, but in that case I would then generate these two frequencies externally, and likely provide the C6748 clock from the same source.

    Dan,

    One option would be to use the PRU subsystem to generate a 150 KHz clock (or 75 KHz clock - I'm not sure which you actually need) in software.  Since the PRU cores can output directly to a pin (when that pin is muxed as a PRU GPO pin), it should be easy to do this and have it feed back into the UPP external clock input pin.  Since the PRU will be clocked at 150MHz when running the core at 300 MHz, the divide down by 1000 or 2000 should be easy to do.

    Regards, Daniel

  • 0 in reply to Daniel Allred
    Expert 1340 points

    Hi Daniel,

    It was actually 150kHz for the DAC output rate, sorry.

    Thanks for presenting another option.

    Dan.