TDA2P-ACD: [TDA2P] TDA2P – EMIF_SDRAM_1 register.

Tomotaroh Kohro

Genius 17265 points

Part Number: TDA2P-ACD

Hello Support team.

I would like to confirm about T_RP bit of EMIF_SDRAM_TIMING_1 register of TDA2P.

Regarding T_RP bit of EMIF_SDRAM_TIMING_1, the below is explanation of TRM.

Minimum number of DDR clock cycles from Precharge to Activate or Refresh, minus one.

When the minimum number of tRP is 13.9 and clock cycle is 1.5ns, what value needs to be set to T_RP bit of EMIF_SDRAM_TIMING_1 ?

KORO

over 4 years ago

+1 Kevin S over 4 years ago

TI__Mastermind 38440 points

Hi,

If tRP is 13.9 ns and the clock cycle is 1.5ns, then T_RP of EMIF_SDRAM_TIMING_1 could be set to a minimum value of 9.

A value of 9 is required as 10 clock cycles are required to satisfy the 13.9 ns, and the parameter should be set to minimum number of DDR clock cycles, minus one.

Best regards,
Kevin

0 Tomotaroh Kohro over 4 years ago in reply to Kevin S

TI__Genius 17265 points

Kevin-san

Thanks a lot.

I got it.

KORO

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TDA2P-ACD: [TDA2P] TDA2P – EMIF_SDRAM_1 register.