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AM5718: How to modify input source clock in AM5718 and TI-RTOS setup

JK
Mastermind 8559 points
Part Number: AM5718

Hi

My customer would like to modify the input source clock from 20Mhz to 19.2Mhz in TI-RTOS setup on top of AM5718 running.

Please describe the detailed steps as possible as you can.

ps. If CTT(Clock Tree Tool) is able to be applicable, Please also mention it.

Thanks.

Best Regards, 

Jack Cha

  • 0
    TI__Guru 50045 points

    Please refer to the below link for notes on custom board addition.

    https://software-dl.ti.com/processor-sdk-rtos/esd/docs/06_03_00_106/rtos/index_board.html#custom-board-addition

    PDK board library for PLL init is based on 20Mhz SYS_CLK so with 19Mhz SYS_CLK, you have to manually update the PLL configuration in Board_PLLInit().

    For TI RTOS, you have to update the GP Timer input frequency from 20Mhz to 19.2Mhz so the OS tick would remain at 1-ms.

    Regards,

    Stanley

  • 0 in reply to Stanley Liu
    Mastermind 8559 points

    Hi Stanley Liu

    Thanks for quick response. 

    I found Board_PLLInit() of evmAM571x_pll.c. 

    Is there a recommended value setting table for 19.2MHz uses case? 

    I understood each of respective DPLL _xxx structure member values are specific for 20MHz input clock. 

    Could you please give me the recommended DPLL_xxx setting table (or combination) for 19.2MHz clock case if available? 

    This is asked since there're no preset values regarding DPLL in the code, And there're no preset when using CTT. since DPLL are bypassed as default.

    Should I tell customer to refer RTOS SDK' Board_PLLInit() code below for for referencing to CTT simulation?  

    Board_STATUS Board_PLLInit()
    {
    pllcMpuParam mpuPllcParam;
    pllcIvaParam ivaPllcParam;
    pllcCoreParam corePllcParam;
    pllcAbeParam abePllcParam;
    pllcDdrParam ddrPllcParam;
    pllcDspParam dspPllcParam;
    pllcGmacParam gmacPllcParam;
    pllcGpuParam gpuPllcParam;
    pllcPcieParam pciePllcParam;
    pllcPerParam perPllcParam;
    CSL_ckgen_prmRegs *hCkgenPrm =
    (CSL_ckgen_prmRegs *) CSL_MPU_CKGEN_PRM_REGS;

    mpuPllcParam.mult = 600U;
    mpuPllcParam.div = 7U;
    mpuPllcParam.dccEnable = 1U;
    mpuPllcParam.divM2 = 1U;
    pllcMpuUnlock();
    pllcMpuConfigure(&mpuPllcParam);
    pllcMpuLock();

    ivaPllcParam.mult = 233U;
    ivaPllcParam.div = 3U;
    ivaPllcParam.divM2 = 3U;
    pllcIvaUnlock();
    pllcIvaConfigure(&ivaPllcParam);
    pllcIvaLock();

    perPllcParam.mult = 0x60U;
    perPllcParam.div = 4U;
    perPllcParam.divM2 = 4U;
    perPllcParam.divM3 = 1U;
    perPllcParam.divH11 = 3U;
    perPllcParam.divH12 = 4U;
    perPllcParam.divH13 = 4U;
    perPllcParam.divH14 = 2U;
    pllcPerUnlock();
    pllcPerConfigure(&perPllcParam);
    pllcPerLock();

    corePllcParam.l3ClkSel = 1U;
    corePllcParam.l4ClkSel = 1U;
    corePllcParam.mult = 0x10AU;
    corePllcParam.div = 0x4U;
    corePllcParam.divM2 = 2U;
    corePllcParam.divM3 = 1U;
    corePllcParam.divH12 = 4U;
    corePllcParam.divH13 = 0x3EU;
    corePllcParam.divH14 = 0x5U;
    corePllcParam.divH22 = 0x5U;
    corePllcParam.divH23 = 0x4U;
    corePllcParam.divH24 = 0x6U;
    pllcCoreUnlock();
    pllcCoreConfigure(&corePllcParam);
    pllcCoreLock();

    hCkgenPrm->CM_CLKSEL_ABE_PLL_REF_REG = 0x00000000U;

    abePllcParam.mult = 0x13U;
    abePllcParam.div = 0x1U;
    abePllcParam.divM2 = 1U;
    abePllcParam.divM3 = 1U;
    pllcAbeUnlock();
    pllcAbeConfigure(&abePllcParam);
    pllcAbeLock();

    gmacPllcParam.mult = 0xFAU;
    gmacPllcParam.div = 0x4U;
    gmacPllcParam.divM2 = 0x4U;
    gmacPllcParam.divM3 = 0xAU;
    gmacPllcParam.divH11 = 0x28U;
    gmacPllcParam.divH12 = 0x8U;
    gmacPllcParam.divH13 = 0xAU;
    pllcGmacUnlock();
    pllcGmacConfigure(&gmacPllcParam);
    pllcGmacLock();

    gpuPllcParam.mult = 170U;
    gpuPllcParam.div = 3U;
    gpuPllcParam.divM2 = 2U;
    pllcGpuUnlock();
    pllcGpuConfigure(&gpuPllcParam);
    pllcGpuLock();

    dspPllcParam.mult = 150U;
    dspPllcParam.div = 3U;
    dspPllcParam.divM2 = 1U;
    dspPllcParam.divM3 = 3U;
    pllcDspUnlock();
    pllcDspConfigure(&dspPllcParam);
    pllcDspLock();

    pciePllcParam.mult = 750U;
    pciePllcParam.div = 9U;
    pciePllcParam.divM2 = 15U;
    pllcPcieUnlock();
    pllcPcieConfigure(&pciePllcParam);
    pllcPcieLock();

    ddrPllcParam.mult = 0x10AU;
    ddrPllcParam.div = 0x4U;
    ddrPllcParam.divM2 = 0x2U;
    ddrPllcParam.divM3 = 0x1U;
    ddrPllcParam.divH11 = 0x8U;
    pllcDdrUnlock();
    pllcDdrConfigure(&ddrPllcParam);
    pllcDdrLock();
    return BOARD_SOK;
    }

    Thanks a lot.

    Best Regards, 

    Jack Cha

  • 0 in reply to JK
    TI__Guru 50045 points

    Yes. Follow the 20Mhz setting as example. Adjust M and N value to get to the same frequency.

    For example, MPU PLL is set to 1500Mhz  = 20 x 600(M) / 8 (N+1) / 1 (M2 divider). In case of 19.2Mhz, 1500Mhz = 19.2 x 625 (M) / 8 (N+1) / 1 (M2 divider).

  • 0 in reply to Stanley Liu
    Mastermind 8559 points

    Hi Stanley

    I told customer as you informed, Let me close this ticket as resolved status. I let customer try it by themselves.

    Many Thanks.

    Best Regards, 

    Jack Cha