PROCESSOR-SDK-OMAPL138: OMAPL138 mDDR interface speed control

Hi

I want to control the interface speed between OMAPL138 and the external mDDR (MT46H64M16LFBF-5 IT:B TR)

I have checked the init file and learnt that I can control the speed by configuring these registers

; This section can be used to configure the PLL1 and the EMIF3a registers
; for starting the DDR2 interface. 
; See PLL1CONFIG section for the format of the PLL1CFG fields.
;            |------24|------16|-------8|-------0|
; PLL1CFG0:  |              PLL1CFG              |
; PLL1CFG1:  |              PLL1CFG              |
; DDRPHYC1R: |             DDRPHYC1R             |
; SDCR:      |              SDCR                 |
; SDTIMR:    |              SDTIMR               |
; SDTIMR2:   |              SDTIMR2              |
; SDRCR:     |              SDRCR                |
; CLK2XSRC:  |             CLK2XSRC              |
;status |= DEVICE_ExternalMemInit(0x000000C5, 0x00134832, 0x264A3209, 0x3C14C722, 0x00000492, 0x00000000);
[EMIF3DDR]
PLL1CFG0 = 0x18010001
PLL1CFG1 = 0x00000002
DDRPHYC1R = 0x000000C4
SDCR = 0x02034621
SDTIMR = 0x20913249
SDTIMR2 = 0x3A1EC7E1
SDRCR = 0x00000492
CLK2XSRC = 0x00000000

But there is no document that shows how to config them, do you have any suggestion for this case?

Thanks

Ryder