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TMS320C6678: I believe there is an error in the documentation:

Mac Radigan
Prodigy 30 points
Part Number: TMS320C6678


RE: TMS320C6678.pdf Multicore Fixed and Floating-Point Digital Signal Processor section 7.6.2.8 Reset Control Register (RSTCFG) field WDTYPE[N] (bits 0-3)

The documentation shows WDTYPE[N] is tied to bits 0-3 for watchdog timer reset 0=Hard Reset and 1=Soft Reset for watchdog timer N.

I have a card with 8 cores, should WDTYPE[N] map to bits 0-7, indicating the watchdog timer for the Nth core?

  • 0
    TI__Guru* 84415 points

    Hello Mac

    Regret the extreme delay in addressing this query. 

    I confirm that your assessment is correct 

    Following updates are needed in the datasheet. 

    RSTYPE (pg 147): WDRST[N] must be from bit 8 to 15 (instead of 8 to 11) and bit 16 to 27 must be reserved (Figure 7-15, Table 7-20) 

    RSTCFG (pg 148 - 149): WDTYPE[N] must be from 0 to 7 (instead of 0 to 3) and bit 8 to 11 must be reserved (Figure 7-17, Table 7-22)

    I will file a literature bug for internal tracking. However I do not have a schedule on when these can be updated to reflect these changes.

    Thank you for bringing this to our attention. This thread will likely lock again in 24 hours, so please feel free to post a new one if you have any follow up queries

    Regards

    Mukul