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C6748 PLL configuration

Tim Sloper
Intellectual 1750 points

The datasheet indicates that an external clock of up to 50 MHz can be used. The datasheet also indicates that the maximum input to the PLL is 30 MHz. On PLL0 this can be met with the pre-divider. The user guide does not indicate there is a pre-divider available for PLL1 yet the PLL configuration spreadsheet does.

Which is correct? If 50 MHz is a valid external input frequency how is it handled by PLL1?

 

Thank you,

Tim

  • 0
    TI__Genius 14545 points

    Tim,

     

    An external clock doesn't make use the on-chip oscillator, so it is not restricted to the frequency range of the oscillator.

     - If you are using an external crystal to clock the device through the oscillator, it can be up to 30MHz crystal.

     - If you are using an external square wave clock, then it can accept a frequency up to 50 MHz.

     

    Once the clock is internal to the device, it doesn't have to use the PLLs, and can be bypassed around the PLLss (directly used). Refer to the clocking diagram for the PLLC's for detailed information.

    Note that the PLL input frequency is spec'd for 30MHz max input - so either way you clock the device, you are limited to a 30MHz input to the PLL.