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AM3505 DDR Simulation - Problem with IBIS Model

Matt C
Prodigy 180 points
Other Parts Discussed in Thread: AM3505

 

Trying to simulate the ddr on the AM3505 with hyperlynx and having some issues with the model. Attached is the file that describes the problems.

Tool:  Using Hyperlynx V8.1.1 (Mentor Graphics)

Device:  AM3505AZCN

Could someone please provide assistance?

Thanks,

-Matt C

  • 0
    TI__Mastermind 43875 points

    Matt,

    It looks like you may have selected either an input sub-model for an output or visa-versa.

    For example, SDRC_D1 calls out selector_16 which has the following sub-models…
    [Model Selector] Selector_16
    Model_100 INPUT,1.8V,HALF_SSTL,+-10%V
    Model_102 3-STATE,1.8V,PI,FAST,+-10%V
    Model_104 INPUT,1.8V,FULL_SSTL,+-10%V
    Model_107 INPUT,1.8V,NONE_SSTL,+-10%V
    Model_113 INPUT,1.8V,HALF_SSTL,+-0.1V
    Model_115 3-STATE,1.8V,PI,FAST,+-0.1V
    Model_117 INPUT,1.8V,FULL_SSTL,+-0.1V
    Model_120 INPUT,1.8V,NONE_SSTL,+-0.1V

    For input simulations one of the input types must be selected based on the input characteristics programmed for the pin.
    For output simulations the 3–state sub-models must be selected. (3-state IOs are of primary type output)

    Some pins have separate input and output sub-models rather than combined IO models.

    BR,

    Steve