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TDA4VM: csitx mipi clock and lane number

subin li
Expert 1050 points
Part Number: TDA4VM

Dear experts,

we are using csitx_transmit_test_main.c to fulfill our own test program about csitx.

1、how to change the mipi clock frequency?

when we set the laneBandSpeed to 800Mbps, we found the mipi clock frequency is 400MHZ;

when we set the laneBandSpeed to 100Mbps, we found the mipi clock frequency is also 400MHZ;

2、in csitx_transmit_test_main.c, App_initTxParams(), appObj->createPrms.instCfg.numDataLanes = 4U

when I change the numDataLanes to 2, I can get the mipi data from 4 lanes, so this change did not take effect.

If I just want to use only two lanes, how should I modify this test code?

thank you

  • 0
    Expert 1050 points

    Dear experts,
    about the question 2, I found a big bug of your source code.
    in CsitxDrv_dphytxLaneReset() of csitx_soc.c
    when set cslDphyCfg.dphyReset = 1, it will only set the DPHY_LN_0_RESET to high. it should reset the lanes we want to use.
    what's more, it directly write CSITX_DPHY_CFG_REG_VAL(0x1F11F) to the DPHY_CFG register(0x04404028).
    this will overwrite our previous configuration.
    I hope you will fix it in the next version of the software, thank you

  • 0
    Expert 1050 points

    Dear experts,

    about the question 1, I didn't find the way to change the mipi clock frequency from the TRM dcoument.

    I don't know which clock source is used.

    In the Figure 12-5690.DPHY_TX0 Environment, what is the source of CSI0_TXCLKN and CSI0_TXCLKP?

    In the Figure 12-5691.DPHY_TX0 Integration,  which clock source is used? the DPHY_TX0_CLK or PSM_CLK or IP2_PPI_C_TXBYTECLKHS?

    How can we reduce the 400MHZ clock？

    thank you

  • 0
    Expert 1050 points

    Dear experts,

    about the question 1, we have already found the way to modify the csitx mipi clock.

    but we found another bug in your csitx driver codes.

    in Csitx_setDphyCfg() of csitx_drv.c, you use Csitx_initDphyCfgParams() to get dphyCfg, but when you set dphy configurations by using Csitx_dphyConfig(), you don't use the dphyCfg you get, you use the instObj get from the global variable “gCsitxCommonObj”.

    so if I change the pllOpDiv in dphyCfg, it won't take effect.

    I hope you will fix it in the next version of the software, thank you

  • 0 in reply to subin li
    TI__Guru**** 478015 points

    Hi Subin li,

    I am sorry for late reply. Let me check and get back to you on these questions. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 1050 points

    Hi，Brijesh

    We also want to know that what is the format of each frame of data sent by csitx.

    If the size of the image we want to send is 1280*960, how much is the line number of the full frame?

    Whether there is front and rear embedded data lines?

    thank you

  • 0 in reply to Brijesh Jadav
    Expert 1050 points

    Hi, Brijesh. Please help answer my last question.

    subin li said:

    We also want to know that what is the format of each frame of data sent by csitx.

    If the size of the image we want to send is 1280*960, how much is the line number of the full frame?

    Whether there is front and rear embedded data lines?

  • 0 in reply to subin li
    TI__Guru**** 478015 points

    Hi Subin Li,

    The format and the size of the frame can be configured in the CSI TX. In the example, the output size is set to 1920x1080 by the macro (APP_TX_FRAME_WIDTH, APP_TX_FRAME_HEIGHT) and format is set to RAW12 by the macro APP_TX_IMAGE_DT. It does not add any other embedded lines, so the frame size provided will be sent out. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 1050 points

    Hi, Brijesh

    Isn’t there some frame start and frame end information?

  • +1 in reply to subin li
    TI__Guru**** 478015 points

    Hi Subin li,

    Yes, there will be frame start and frame end, but it is added by TX module, Application does not require to explicitly add it.

    Regards,

    Brijesh