TMS320C6748: Timer Problem

Hi Yusuf,

Just to make sure I understand your question, you have the ISR fired for every pulse which is @ 1 second rate. You are noticing the ISR spacing as 1,000,027 micro seconds.. and you are chasing the reason for additional 27 micro seconds right?

Yusuf Furkan Yucesoy said:

Also instead of measuring time intervals. I decided to measure the number of ticks for each second. For the 300 Mhz clock source, while the processor is expected to make about 300.000.000 tick, I always get values ​​like 300.008.500.

I am wondering, why are you expecting your clock source be a perfect clock? They would have jitter and if I read the above right, you are chasing the reason for 300,008,500 ticks. About 8500 ticks . Note that the TSC ticks for every CPU cycle.

It makes me think you are running your CPU at 300,008,500Hz. Is it possible for you to double check this and see if you are running the CPU at slightly higher clock?

By the way, is this on the LCDK EVM or your own custom board having the TMS320C6748  chip?

Thanks

Aravind Batni said:

Just to make sure I understand your question, you have the ISR fired for every pulse which is @ 1 second rate. You are noticing the ISR spacing as 1,000,027 micro seconds.. and you are chasing the reason for additional 27 micro seconds right?

Yes that is exactly the case.

Aravind Batni said:

I am wondering, why are you expecting your clock source be a perfect clock? They would have jitter and if I read the above right, you are chasing the reason for 300,008,500 ticks. About 8500 ticks . Note that the TSC ticks for every CPU cycle.

It makes me think you are running your CPU at 300,008,500Hz. Is it possible for you to double check this and see if you are running the CPU at slightly higher clock?

I dont expect the clock source to work perfectly. But constantly working more than expected creates a problem. Also I think I have set the PLL settings correctly. I did tests not only with 300 Mhz clock source but also with with dirrefent frequencies (1 Mhz, 50 Mhz, 100 Mhz etc.) But all the time I got more tick count than expected from TSC.

Aravind Batni said:

By the way, is this on the LCDK EVM or your own custom board having the TMS320C6748  chip?

I have my own custom board.

Hi Yusuf,

Thanks for the details and confirmation. 

Can you please provide more details on how are you capturing the tick counts and measuring the 1second window? 

By the way, is it possible for you to read the TSC register and drive a GPIO pin (output) high and after some time read the TSC and drive that pin to low and measure the time and TSC cycles?

Basically, can you please rule out if you are be running the CPU at a slightly higher clock rate?  I have not heard anytime TSCL going out of sync with CPU cycles.

Thanks

Hi Yusuf,

I did the above experiment myself and noticed no issues on the TSC values. 

The experiment that I did is below:

1. set up a periodic timer interrupt and capture the TSCL, each time the ISR fires in the timer ISR

2. Toggle a GPIO pin in the Timer ISR each time

3. Read the TSCL value into an arrary

4. Compute the difference between each read

Observation:

I see the timer getting fired for every 80ms and the TSCL delta shows the values around 300Mhz as below: (note the jitter around it).

Please note that there is minor software jitters as well contributing to this. (handling interrupt service routine etc)

Please click the below to get the picture pop up.

Aravind Batni said:

Can you please provide more details on how are you capturing the tick counts and measuring the 1second window? 

Every time the ISR runs, I take the time information from the TSC registers and put it into an array. Then I calculate the intervals between the elements of this array. Actually, I can say that it works with the math "present - previous = interval ".

Aravind Batni said:

By the way, is it possible for you to read the TSC register and drive a GPIO pin (output) high and after some time read the TSC and drive that pin to low and measure the time and TSC cycles?

Actually, I've done an experiment close to the experiment you mentioned before. I toggled one gpio pin every time in the interrupt service routine. I compared the signals on my interrupt input pin and the gpio pin that I toggle with the oscilloscope. I could not see a difference (error condition) between these two signals. This means that the problem is reading the time data in TSC.

Aravind Batni said:

set up a periodic timer interrupt and capture the TSCL, each time the ISR fires in the timer ISR

I think there was a wrong approach in your experiment. As I understand it, your interrupt source is an internal structure. You need to understand whether there are any errors in the structure and use an external time source. Otherwise, since your  time reference is internal, it is not possible to catch the error condition.

Hi Yusuf,

My time measurement is not internal. Yes, I am using the timer (dmTimer - internal timer) to enter into the ISR and I read the TSC in the ISR. But, note that I am outputting the GPIO toggle signal from the ISR to external Logic Analyzer and I am measuring the absolute time difference externally (the time pin stays high Or the time pin stays low) to check the counted TSC ticks.

I do not see an issue in my experiment, since I am measuring the actual time externally for the accumulated TSC cycles.

Thanks

Hi Aravind,

As I understand, my intervals that I calculate from TSC are in acceptable scope. Also in your experiment average frequency is 300.002471231156 so average tick count 300 002 471 in a second on  the processor. Would not the average tick count be expected to be closer to 300 000 000?

Many thanks for your interest

Hi Aravind,

Thank you very much for all your answers and interest.