AM5718: How to change U-boot when change OSC source clock from 20Mhz to 19.2Mhz?

Hi

My customer uses AM5718 and Linux SDK. And they would like to change OSC input from 20MHz to 19.2Mhz for their custom board.

Could you please clarify where to change input source clock from 20MHz to 19.2Mhz. ?

I tried to find out the relevant code change from  "arch/arm/mach-omap2/omap5/hw_data.c".

And I found the structure definition and usage are below.

I see the various preset values are already defined in the sdk code.But I could not find where to indicate the selected clock among that supported array combination. 

Please let me know how a specific clock combination is selected among 7 set of mpu_dpll_params_1ghz. 

I mean how does 19.2Mhz case is selected?

/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};

struct dplls dra76x_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra76x,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2664mhz,
.gmac = gmac_dpll_params_2000mhz,
};

struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2128mhz,
.gmac = gmac_dpll_params_2000mhz,
};

struct dplls dra72x_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2664mhz,
.gmac = gmac_dpll_params_2000mhz,
};

void __weak hw_data_init(void)
{
u32 omap_rev = omap_revision();

...

case DRA762_ABZ_ES1_0:
case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra76x_dplls;
*ctrl = &dra7xx_ctrl;
break;

case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
break;

case DRA722_ES1_0:
case DRA722_ES2_0:
case DRA722_ES2_1:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
*ctrl = &dra7xx_ctrl;
break;

...

}

Thanks a lot.

Best Regards,

Jack Cha