Hi,
I am using TMS320C6678 multi-core DSP.
As per hardware design guide for keystone I chips (SPRABI2D), all the differential clock inputs (CORE/PASS/DDR - CLKs) are designed using LJCBs which include 100 ohms differential termination and common-mode biasing.
When I did simulation of these clocks, it looks to me that the IBIS models of this clocks don't include the 100 ohms termination, because the waveforms are appearing very poor without external termination. Can someone verify if the terminations are missing or present in the IBIS model?
Thanks,
Binayak