AM6442: GPMC non-multiplexed address data

Hi Rei,

Your calculations are correct.

On AM64, with GPMC in non-mux mode there are 23-bits for the address, 2^23 = 8MB. 8MB is the maximum for each CS. With 4CS, there is 32MB total.

With GPMC in AD-mux mode and 32-bit data bus, there are 26-bits for the address to a 32-bit word, 2^26 * 4 bytes = 256MB maximum for each CS (256MB > 128MB!). With 4CS, there is on paper 1024MB total (1024MB >> 128MB!)

Similarly with GPMC in AD-mux mode and 16-bit data bus, there are 26-bits for the address to a 16-bit word, 2^26 * 2 bytes = 128MB maximum for each CS. With 4CS, there is on paper 512MB total (512MB > 128MB!)

But the GPMC is memory mapped to the CPU byte address from 0x050000000 to 0x057FFFFFF (128MB). This memory map range is divided among the available chip selects.
Example 1) CS0 uses the entire 128MB
Example 2) CS0, 1, 2, 3 evenly divide the 128MB, so each CS can use 32MB
Other combinations are possible.

The chip-select size is programmable from 16MB to 256MB (must be a power-of-two) and is defined by the mask field (GPMC_CONFIG7_i[11-8] MASKADDRESS)

The GPMC_CONFIG7_i[5-0] BASEADDRESS bit field maps the CPU byte address from 0x050000000 to 0x057FFFFFF to the 4 available chip selects.

Refer to AM64 TRM 12.3.3.4.7.1 Chip-Select Base Address and Region Size

Regards,
Mark