Hi,
I'm looking for advice on reducing what appears to be high conducted harmonics from the PLL on a custom C5505 based board.
The system PLL clock is programmed to 100MHz at boot time and it is at this point that we observe high harmonics on the 1.3V VCORE power supply. The voltage is measured on a VCORE test point with a soldered-on U.FL connector and a short coaxial, and observed with a spectrum analyzer. Fundamental is low, but harmonics 20 - 30 dB relatively higher. Other 3V3 system supply shows similar, but slightly different harmonic redistribution, overall higher harmonics than the fundamental …
The VCORE supply to the C5505 device is well decoupled and includes series ferrite beads on the PLL supply input and PLL Vss pins. Additional 470pF decoupling capacitors with < 150mΩ ESR added but no apparent reduction in harmonics of 100MHz. Overall based on the schematic from a TI C5505 EVM demo board…
Generally speaking, probing with a near-field probe shows the PLL EMI harmonics around the DSP device case and around the 3V3 switcher supply, and the 1.3V VCORE LDO supply. However, after some further evaluation, the third harmonic on the 1.3V supply seems to reduce by 20dB with the addition of a 470pF decoupling on the device RESET line... Other higher harmonics not effected as such, even with the addition of a 150pF in parallel over the 470pF ...
This begs the question what device pin(s) may possibly be leaking and/or require additional targeted decoupling/filtering to reduce PLL unwanted EMI observed on VCORE supply using the SA ??
Having said this, conducted measurements may not directly translate to unwanted emissions, but some preliminary evaluations of EMI emissions in a chamber suggest that PLL harmonics at around 5th and 6th harmonic of the PLL could present a problem for EMC certification, so in essence, it is envisaged that firstly reducing these conducted, measured harmonics around the source, will translate to equally reduced EMI far-field emissions in a suitably equipped chamber.
No other observable EMI other than the PLL system clock source presenting potential problems as yet.
Any suggestions advice would be highly appreciated.
Regards, citiZen
