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CMOS sensor to DM365 issues

For the CMOS sensor, we are estimating whether the problem is from latching data from pixel clock's rising edge or falling edge. However, I can't search this setting, so I would like to ask how could I set the data latch status? 1. The video output would be disabled when the AV Server is initialized, but it won't exist when we run this in IPNC. Would this caused by the running frequency of ARM(216MHz for our board, 297MHz for IPNC board)? If I comment the following codes from int DRV_vpssInit() function, the video output would still running even AV Server is initialized. DRV_SyncRst(47, 0, 0); DRV_SyncRst(47, 0, 3); >>> 2. After comment these two codes, I am going to test our cmos sensor. However, we found that it hangs when it execute "DRV_isifWaitInt(DRV_ISIF_INT_VD0, 2);", and cmos sensor output the valid Vsync, Hsync, PCLK and Data to TI. >>> 3. I found that the RTC didn't run at all, and the log shows "rtc wait time out !!!!!" when the kernel start up. The PWRST and PWRCNTON pins are high, and RTCX1 is running in 32.7k.

  • Elan,

    It is very hard for me to catch your questions with your layout format. I would suggest to have more paragraphs in your future post.

    Anyway, pls find my answer for your fisrt quesiton below.

    1. The Clock controller can configure to trigger on the rising or falling edge of the PCLK signal by setting the bit VPSS_CLK_CTRL.PCLK_INV in SYSTEM module registers. You can find below in ARM subsystem guide.

    VPSS Clock Mux Control (VPSS_CLK_CTRL) Register

    Bit    Field              Value      Description
    2      PCLK_INV                     Video encoder PCLK polarity
                                   0               VENC clk mux receives normal PCLK
                                   1               VENC clk mux receives inverted PCLK