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Original question:

AM572x DDR Memory Configuration

AM572x bld Configuration Parameters

Hidekazu
Intellectual 880 points

Hi,expert

I am tuning the bld file(C:\ti\pdk_am57xx_1_0_17\packages\ti\build\am572x\Config_xxxx.bld),
 but in what cases the following cache-related settings (3 SIZE) are needed. Will you judge?
What are the benefits of setting this value?
Could you please explain the details with a concrete example?

APP_CACHED_DATA_BLK1_SIZE = 122*MB;
APP_CACHED_DATA_BLK2_SIZE = 64*MB;
APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;

Best Regards,
Hidekazu

  • 0
    TI__Guru 50045 points

    Hi,

    These are 3 different memory regions in DDR.

    First two are cache-enabled regions and the third one is non-cached region.

    Cache configuration should be set up accordingly.

    It is just the way the DDR memory is organized for PDK examples to use.

    You don't have to follow this for your application.

    You can specify the memory region size based on your application needs.

    Regards,

    Stanley