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TDA4VM: Inline ECC Error Injection Test

Part Number: TDA4VM

Hello,experts,

I'm try to enable inline ecc for DDR in TDA4.

I want to know if the DDR controller supports poison feature and how to do the error injection test.

Can you give me some suggestions?

Best Regards,

Nathan

  • Hi Nathan,

    There is an error test for DDR inline ECC available in the csl ecc_test_app:
    pdk/packages/ti/csl/example/ecc/ecc_test_app/ecc_ddr.c
    Note that the method cannot be used in a real application, because it involves temporarily disabling the ECC in order to corrupt the memory

    Regards,
    Keerthy

  • Hi,Keerthy,

    Thanks for your response.I have three new questions about inline ECC.

    1. Do you have user guide about this example? I have compiled this example successfully, but when I put image on the evm board, there is no output from MCU UART.

    2. How should I measure the impact of enabling ECC about bandwidth and latency?

    3. When Ecc is enable, one ninth DDR is used for storing ECC syndromes.If DDR size is 4GB with ECC ON, DDR available is 3640MB.Can we reduce the size of DDR used for storing ECC syndromes?

    Best Regards,

    Nathan

  • Hi Nathan,

    We got answers from our internal team.

    1. No, there is no user guide for the example.
    2. I believe there was a ppt that was circulated to DJI on the impact analysis.
    3. That is not possible as 1/9th is expected to be reduced.

    - Keerthy

  • Hi Keerthy,

    Thanks for you reply.

    Best Regards,

    Nathan