PROCESSOR-SDK-J721E: QoS for DDR accesses

Michael Fainstein

Part Number: PROCESSOR-SDK-J721E
Other Parts Discussed in Thread: DRA829, TDA4VM

J721e MSMC has "Two-level QoS support for real-time/nonreal-time split" and DDRSS has "Priority based scheduling" and "Class of Service (CoS) - Three latency classes supported".
However, default setup is "fair" scheduling of accesses to DDR. So, when I ran real-time code on CPU that I designated as "RT CPU", memory accesses of other CPU get their "fair" share of bandwidth to DDR, reducing execution speed of RT-CPU and creating jitter in interrupt latency.
How can I change setup to give priority to A72's core1 over core0 or R5F over A72, i.e., how do I tell J721e that core1 (or R5F) is RT-CPU and must use "strict" priority for memory accesses?
The documentation in "J721E DRA829/TDA4VM Processors Silicon Revision 1.1 Texas Instruments Families of Products - Technical Reference Manual" is not clear.

Thank you,
Michael

over 5 years ago

0 Kevin S over 5 years ago

TI__Mastermind 44190 points

Hi Michael,

From DDR perspective, my understanding is the following parameters should enable priority scheduling per command. (based on QOS)

DDRSS_CTL_276[0] (PRIORITY_EN) = 1
DDRSS_CTL_377[24] (AXI0_FIXED_PORT_PRIORITY_ENABLE) = 0

We are trying to follow-up on configuring QOS within the SOC.

Thanks,
Kevin

0 Kevin S over 5 years ago in reply to Kevin S

TI__Mastermind 44190 points

Hi Michael,

My understanding is that J721E cannot change the priority of A72 core 1 over A72 core 0. Instead, it can only prioritize the whole cluster over other traffic.

A few suggestions from our internal team:

Make everything very high priority from A72
Use SRAM for real-time core execution

Thanks,
Kevin

0 Michael Fainstein over 5 years ago in reply to Kevin S

Intellectual 400 points

Hi Kevin,

is it possible to give priority to R5F over A72? How?

Thanks,

Michael

0 Kevin S over 5 years ago in reply to Michael Fainstein

TI__Mastermind 44190 points

Hi Michael,

My understanding is that the R5 can be prioritized over the A72; however, I have not already invested time here to be able to confirm that understanding and answer your second question of "How?".

I am trying to follow-up with others internally to help answer this question.

Thanks,
Kevin

0 Michael Fainstein over 5 years ago in reply to Kevin S

Intellectual 400 points

Hi Kevin,

I am still waiting on "How to prioritize R5F over A72 for memory accesses"

Thanks,

Michael

0 Kevin S over 5 years ago in reply to Michael Fainstein

TI__Mastermind 44190 points

Hi Michael,

I apologize, my understanding is that TI has been communicating with your company outside of E2E so this thread may have lost traction.

Note that I am re-assigning to someone else who may have more knowledge on the subject matter.

Best regards,
Kevin

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PROCESSOR-SDK-J721E: QoS for DDR accesses