Other Parts Discussed in Thread: SYSBIOS, AM6421
Hi Ti,
I would like to use PCIe to communicate between multiple TDA4-SoCs. Basically, I try to implement the proposal which was posted here:
I've experimented with PCIe and Linux and came to conclusion that due to linux scheduler mechanizm (TI does not support Linux RT Kernel for TDA4, "only" preemptive patched) the jitter of PCIe transaction is for our cases to high. Especially if the device receives network data, which has high/er/est priority compared to kernel work queues.
Therefore I try to implement a "kind of Non-Transparent-Bridge"-Solution with TI PCI LLD, which uses SysBios and runs on dedicated R5F to hopefully improve determinism and decrease jitter times.
There exists a PCIe example for AM65, I used that code and got the example running on two TDA4VMEVM. Data transfer between RC and EP without UDMA works.
I try to dig into PCIe Gen3 Specification, the functionality of TDA4 PCIe-modules but there are some questions left, which I hope you can provide me some support.
I think the the recent version of TRM Chapter PCIe Subsystem is incomplete and the PCIe LLD is still under development.
Q1: At some LLD code, I stumbled over comments which refer to "rev1 hw rev2 hw". Example: /drv/pcie/pcie.h Line 10504
/** * @brief [rw] Region Index * * On rev 1 hw, this corresponds to REGION_INDEX * On rev 2 hw, this is virtual sw register to demux 16 inbound/outbound regions * * Outbound region, from 0 to 15. * Inbound region, from 0 to 3 (rev 1) or 0 to 15 (rev 2) * * Field size: 4 bits */ uint8_t regionIndex; } pciePlconfIatuIndexReg_t; /* @} */
Which "hw rev" is implemented in TDA4 and AM6421?
Q2: How do I access/configure physical functions with the LLD? I need multiple physical functions on the same PCIe module. After my first glance in the LLD code I get impression that this is not supported. At some configuration functions there is always refered hardcoded to physical function 0. Example: /drv/pcie/src/v3/pciev3_plconf.c Line 365
/*****************************************************************************
* Combine and write the PL CONF iATU Region Lower Base Address register
****************************************************************************/
pcieRet_e pciev3_write_plconfIatuRegLowerBase_reg
(
CSL_pcie_ep_coreRegs *baseAddr,
const pciePlconfIatuIndexReg_t *simIatuWindow,
pciePlconfIatuRegLowerBaseReg_t *swReg
)
{
uint32_t new_val = swReg->raw;
pcieRet_e retVal = pcie_RET_OK;
/* Don't need to check NULL this is internal API */
uint8_t regionIndex = simIatuWindow->regionIndex;
pcie_range_check_begin;
if (regionIndex < 16)
{
if (simIatuWindow->regionDirection == 0U)
{
/* 0U == OUTBOUND */
pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_DATA, swReg->iatuRegLowerBase);
pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_WRAPPER_OB_0_ADDR0_NUM_BITS, swReg->zero);
swReg->raw = baseAddr->ATU_WRAPPER_OB[regionIndex].ADDR0 = new_val;
}
else
{
/* INBOUND */
pcie_setbits(new_val, CSL_PCIE_EP_CORE_ATU_FUNC0_WRAPPER_IB_EP_0_ADDR0_DATA, swReg->iatuRegLowerBase);
swReg->raw = baseAddr->ATU_FUNC_WRAPPER_IB_EP[0][regionIndex].ADDR0 = new_val<<8;
retVal = pcie_range_check_return;
}
}
else
{
retVal = pcie_RET_RANGECHK;
}
return retVal;
} /* pciev3_write_plconfIatuRegLowerBase_reg */
During configuring iATU: ATU_FUNC_WRAPPER_IB_EP[0] <- Hardcoded index 0 ? Maybe I am wrong here.
Q3: Following Screenshot is from TRM:
For me, it is not clear whats the difference between group 1 and group2, and between group 3 and 4.
There are 16 instances of group 1 and 2. Are they refering to virtual functions? If yes, how do I assign them to a specific virtual function?
There are 3 instances of group 3. Whats the purposes of these?
And finally there are 16 * 8 instances of group 4. I guess these belongs to specific virtual function + BAR idx?
Thank you very much for support in advance.. I think there might come up more questions 
Best regards,
Thomas
