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[DRA821]Questions about DDR initialization

Linda Xie
Intellectual 450 points

Other Parts Discussed in Thread: DRA821

Hi,Experts

    We use the Sciclient_pmDeviceReset function to perform the reset of DRA821 in xSpi boot mode and the Soc is correctly reset. However, after the reset, SBL will stay at line 109 of Board_DDRChangeFreqAck function, so the App cannot be executed normally after the reset.What is this probably about?

    Looking forward to your reply soon!

    Regards,

   Xie

  • 0
    TI__Guru* 78145 points

    Hi Xie,

    Can you please confirm which SDK version are you using? We had a similar bug on another platform which is getting fixed in the upcoming release and I want to confirm if this could be the same.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    Intellectual 450 points

    Hi,Karan

         The SDK version is ti-processor-sdk-rtos-j7200-evm-07_01_01_10.

        I have another question, we use DRA821 xSPI boot mode, call Sciclient_pmDeviceReset function in APP to reset SOC, but after reset he stops at 0x4180178C address every time, I check TRM and find that it stays in ROM code, do you know what is the reason when this happens?

     Regards,

      Xie

  • 0 in reply to Linda Xie
    TI__Guru* 78145 points

    Hi Xie,

    There was a bug for another platform which got fixed in this release, I'm checking if that applies to DRA821 too.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    TI__Guru* 78145 points

    Hi Xie,

    Had an offline discussion on this and seems like the issue (atleast on the EVM) gets resolved from the patch attached.

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_sbl_2D00_it_2D00_can_2D00_not_2D00_bypss_2D00_DDR_2D00_PLL_2D00_after_2D00_warm_2D00_reset.patch

    But if I understand correctly, there is still an issue on the custom board. Correct?

    Can you add a while(1) loop before the DDR init after warm reset and then connect JTAG, get out of the while(1) and then debug and see what is getting executed on the R5F?

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    Intellectual 450 points

    Hi,Karan

        The DDR patch has been given to me by Zhang Fan, and it has been verified on EVM, but the one on our board seems to be a different problem.

       I did try on three boards every time after warm reset it stays at ROM Code (address is 0x4180178C), can you analyze the reason from ROM Code?

    Regards,

    Xie

        

  • 0 in reply to Linda Xie
    TI__Guru* 78145 points

    Hi Xie,

    Can you check connect CCS before executing the DDR init code and step through to see how we land up at 0x4180178C address?

    Regards,

    Karan