Other Parts Discussed in Thread: AM6548
Hi all,
maybe a silly question, i had Interrupt Level routing configured and working to get PRU Interrupts to R5F domain on out AM6548 platform using TiRTOS before. Now we switched from PDK 1.0.7 to PDK 7.1.0.55 and the setup of IRQ routing does not work anymore.
It looks like it is depending to the DMSC firmware package. When using PDK1.0.7 binaries and the launch.js from PDK 7.1.0.55 with the DMSC firmware from 7.1.0.55 i get a Data Abort exception in the TI code.
/* Initialize Main to MCU Interrupt Router config structure */
intrRouterMain2MCUCfg.pIntrRouterRegs = (CSL_intr_router_cfgRegs *)(uintptr_t)(CSL_MAIN2MCU_LVL_INTRTR0_CFG_BASE);
intrRouterMain2MCUCfg.pIntdRegs = (CSL_intr_router_intd_cfgRegs *)(uintptr_t)NULL;
intrRouterMain2MCUCfg.numInputIntrs = 192;
intrRouterMain2MCUCfg.numOutputIntrs = 64;
for (index = 0; index < (sizeof(pruIntRtrOutIntNum)/sizeof(pruIntRtrOutIntNum[0])); ++ index)
{
CSL_intrRouterCfgMux(&intrRouterMain2MCUCfg, pruIntRtrInIntNum[index], pruIntRtrOutIntNum[index]);
}
the exception occurs in CSL_intrRouterCfgMux:
int32_t CSL_intrRouterCfgMux(CSL_IntrRouterCfg *pCfg, uint32_t inputIntrNum, uint32_t outputIntrNum)
{
int32_t retVal = 0;
if((outputIntrNum < pCfg->numOutputIntrs) && (inputIntrNum < pCfg->numInputIntrs))
{
uint32_t regVal;
/*---------------------------------------------------------------------
* An interrupt enable bit (bit 16) was added to version 1.0.16.0
* of the interrupt router that enables generation of the external
* interrupt. The following sequence is required when configuring
* the mux to insure glitch-free operation.
*
* Note that disabling/enabling the interrupt has no affect on ealier
* versions of the interrupt router, so we perform these operations
* regardless of IP version.
*-------------------------------------------------------------------*/
regVal = CSL_REG32_RD( &pCfg->pIntrRouterRegs->MUXCNTL[outputIntrNum] );
/* Disable interrupt output */
regVal &= ~INTR_ROUTER_CFG_MUXCNTL_INT_ENABLE;
CSL_REG32_WR( &pCfg->pIntrRouterRegs->MUXCNTL[outputIntrNum], regVal );
/* Configure mux value */
CSL_FINS( regVal, INTR_ROUTER_CFG_MUXCNTL_ENABLE, inputIntrNum );
/* EXCEPTION HERE: */
CSL_REG32_WR( &pCfg->pIntrRouterRegs->MUXCNTL[outputIntrNum], regVal );
/* Enable interrupt output */
regVal |= INTR_ROUTER_CFG_MUXCNTL_INT_ENABLE;
CSL_REG32_WR( &pCfg->pIntrRouterRegs->MUXCNTL[outputIntrNum], regVal );
}
else
{
retVal = -1;
}
return retVal;
}
the assembler code of the CSL_REG32_WR did not change with new PDK and the access looks fine for me:
ldr r2, [r3, #4]
bic r2, r2, #0x10000
str r2, [r3, #4]
the str call asserts the data abort exception: r3 = 0xa10008, r2 = 0x42
writing the 0x42 using memory view in ccs works fine (also does working different values back and forth), currently i am puzzled about what is going on there. What in fact could impact from changing the dmsc firmware.
