Part Number: AM4372
Other Parts Discussed in Thread: DP83867IR
Hello,
our customboard is based on a am437x-EVM board, but uses the DP83867ir PHY to support 1Gbit-Communication.
The ROM-Bootloader is able to load the SPL-Bootloader over Ethernet. After that, the SPL-Bootloader tries to send BOOTP-Requests to the Host-PC to load the Bootloader.
It seems that the Board is not sending any data, i cant see any communication on wireshark or over the status leds. I tried to Configure the PHY with 100Mbit and 1000Mbit but booth variants do not work.
Console Output:
U-Boot SPL 2018.01 (Apr 01 2021 - 17:50:50)
Trying to boot from eth device
*** Warning - bad CRC, using default environment
cpsw
cpsw Waiting for PHY auto negotiation to complete.... done
link up on port 0, speed 100, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17
Retry time exceeded; starting again
Problem booting with BOOTP
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Pin Declaration:
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_col), MODE(0)| RXACTIVE}, /* GMII1_COL */
{OFFSET(mii1_crs), MODE(0)| RXACTIVE}, /* GMII1_CRS */
{OFFSET(mii1_rxerr), MODE(0)| RXACTIVE}, /* GMII1_RXER */
{OFFSET(mii1_txen), MODE(0)}, /* GMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* GMII1_RCTL */
{OFFSET(mii1_txclk), MODE(0)| RXACTIVE}, /* GMII1_TxCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* GMII1_RxCLK */
{OFFSET(mii1_txd3), MODE(0)}, /* GMII1_TD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* GMII1_TD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* GMII1_TD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* GMII1_TD0 */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* GMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* GMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* GMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* GMII1_RD0 */
{-1},
};
static struct module_pin_mux mdio_pin_mux[] = {
{OFFSET(mdio_data), MODE(0) | RXACTIVE},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0)}, /* MDIO_CLK */
{-1},
};
Ethernet Initialization:
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_if = PHY_INTERFACE_MODE_RGMII,
.phy_addr = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_if = PHY_INTERFACE_MODE_RGMII,
.phy_addr = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
uint32_t ctrl_val;
int rv = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!env_get("ethaddr")) {
puts("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
writel(RGMII_MODE_ENABLE, &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0) {
printf("Error %d registering CPSW switch\n", rv);
return rv;
}
#endif
return rv;
}
Defines to support ethernet boot
#define PHY_ANEG_TIMEOUT 8000 #define CONFIG_DRIVER_TI_CPSW #define CONFIG_PHY_TI #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_SYS_RX_ETH_BUFFER 64
I am currently out of ideas what the problem could be.
I've already checked if the pin configuration is correct.
After the generec phy-configurations the dp83867 driver in /drivers/net/phy/ti.c is being used.
Are there any suggestions what to do next? How does the ROM-Bootloader handle this?
