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TDA4VM: Broadcast packets not being passed through hardware switch

Spencer Hill
Prodigy 110 points
Part Number: TDA4VM
Other Parts Discussed in Thread: DP83867E

Hello,

We are attempting to connect two devices over Ethernet using the TDA4's internal switch and are experiencing issues getting it fully working.

We are using Processor SDK version 07.00.00.11.

Linux is using the virt-mac driver to access the CPSW9G

R5F0_0 is running the merged EthFw + vision_apps code

Several CPSW9G ports are hooked up to DP83867E PHYs

At the moment, it seems as if broadcast packets are not being sent through the switch. DHCP packets are visible on one side of it, and are not being received on the other.

If static IP addresses are configured, it is possible to ping from the J7 to the other devices it is connected to (a laptop and another board) using these static IP addresses, however other broadcast packets are still lost.

We've looked at most of the settings for the ALE and they seem to be set up correctly.

If you have any advice on where to look for what might be the cause of broadcast packets being lost that would be very helpful.

Thank you.

  • 0
    TI__Mastermind 37435 points

    Hi,

    Broadcast to other MAC ports should be supported out of the box. I will check and let you know.

    Can you tell me if

    1. You have an EVM to test ?

    2. Any plans to migrate to SDK 7.2 or newer ?

    Regards

    Vineet

  • 0
    TI__Mastermind 37435 points

    Hi,

    Can you confirm that you are trying to use the CPSW 9G like any ordinary switch ? By that I mean connecting multiple devices on it's physical ports and then expecting broadcast packets going between them ?

    Regards

    Vineet

  • 0
    Prodigy 110 points

    Hello,

    We are using the CPSW 9G like an ordinary switch, there are no special cases or filtering in our setup, just multiple physical devices connected together through it. At the moment we don't have any plan to change SDK versions.

  • 0
    TI__Mastermind 37435 points

    Hi Spencer,

    Can you run the debug gels specified in this link and attach the output ? When BC packets are being sent to device.

    Regards

    Vineet

  • 0
    Prodigy 110 points

    Here are the outputs from running those debug scripts.

    stats print reg
MAIN_Cortex_R5_0_0: GEL Output:           STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT0 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_RXGOODFRAMES              = 0x00000155
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_RXBROADCASTFRAMES         = 0x00000006
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_RXMULTICASTFRAMES         = 0x00000027
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_ALE_DROP                  = 0x00000027
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_RXOCTETS                  = 0x000076B0
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_TXGOODFRAMES              = 0x00000130
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_TXBROADCASTFRAMES         = 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_TXOCTETS                  = 0x000067FE
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_OCTETFRAMES64             = 0x00000023
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_OCTETFRAMES65T127         = 0x00000248
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_OCTETFRAMES128T255        = 0x00000011
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_OCTETFRAMES256T511        = 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_OCTETFRAMES512T1023       = 0x00000006
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_NETOCTETS                 = 0x0000DEAE
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_PORTMASK_DROP             = 0x00000027
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_TX_PRI_REG             [6]= 0x00000130
MAIN_Cortex_R5_0_0: GEL Output: STAT_0_TX_PRI_BCNT_REG        [6]= 0x000067FE
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT1 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT2 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT3 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT4 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT5 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT6 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT7 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_RXGOODFRAMES              = 0x000001C0
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_RXBROADCASTFRAMES         = 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_RXMULTICASTFRAMES         = 0x00000090
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_ALE_DROP                  = 0x00000090
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_RXOCTETS                  = 0x000136A4
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_TXGOODFRAMES              = 0x0000012E
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_TXBROADCASTFRAMES         = 0x00000006
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_TXOCTETS                  = 0x0000634C
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_OCTETFRAMES64             = 0x00000023
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_OCTETFRAMES65T127         = 0x00000230
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_OCTETFRAMES128T255        = 0x00000002
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_OCTETFRAMES256T511        = 0x00000093
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_OCTETFRAMES512T1023       = 0x00000006
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_NETOCTETS                 = 0x000199F0
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_PORTMASK_DROP             = 0x00000090
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_ALE_UNKN_UNI              = 0x00000018
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_ALE_UNKN_UNI_BCNT         = 0x000008D2
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_ALE_UNKN_MLT              = 0x00000008
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_ALE_UNKN_MLT_BCNT         = 0x00000B80
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_ALE_UNKN_BRD              = 0x00000001
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_ALE_UNKN_BRD_BCNT         = 0x000000F5
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_ALE_POL_MATCH             = 0x0000012B
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_TX_PRI_REG             [0]= 0x0000012B
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_TX_PRI_REG             [1]= 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_TX_PRI_BCNT_REG        [0]= 0x00005E68
MAIN_Cortex_R5_0_0: GEL Output: STAT_7_TX_PRI_BCNT_REG        [1]= 0x000004E4
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output:           PORT8 STATS          
MAIN_Cortex_R5_0_0: GEL Output: --------------------------------
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TXGOODFRAMES              = 0x00000025
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TXBROADCASTFRAMES         = 0x00000009
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TXOCTETS                  = 0x00001342
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_OCTETFRAMES64             = 0x00000006
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_OCTETFRAMES65T127         = 0x00000018
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_OCTETFRAMES128T255        = 0x00000002
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_OCTETFRAMES256T511        = 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_OCTETFRAMES512T1023       = 0x00000002
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_NETOCTETS                 = 0x00001342
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TX_PRI_REG             [0]= 0x0000001F
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TX_PRI_REG             [1]= 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TX_PRI_REG             [6]= 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TX_PRI_BCNT_REG        [0]= 0x00000B68
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TX_PRI_BCNT_REG        [1]= 0x000004E4
MAIN_Cortex_R5_0_0: GEL Output: STAT_8_TX_PRI_BCNT_REG        [6]= 0x000002F6


mdio_config : phy alive
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: PHY ALIVE STATUS 
MAIN_Cortex_R5_0_0: GEL Output:  PHY 0 (0x00000000)
MAIN_Cortex_R5_0_0: GEL Output:  PHY 1 (0x00000001)
MAIN_Cortex_R5_0_0: GEL Output:  PHY 2 (0x00000002)
MAIN_Cortex_R5_0_0: GEL Output: PHY LINK STATUS 
MAIN_Cortex_R5_0_0: GEL Output:  PHY 2 (0x00000002)

mdio_config : phy 0 reg
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 0  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00001140 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 1  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00007949 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 2  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00002000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 3  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x0000A231 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 4  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x000001E1 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 5  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 6  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000064 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 7  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00002001 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 8  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 9  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000300 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 10  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 11  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 12  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 13  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 14  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 15  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00003000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 16  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00005848 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 17  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000002 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 18  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 19  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000040 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 20  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x000029C7 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 21  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 22  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 23  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000040 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 24  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00006150 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 25  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00004444 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 26  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000002 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 27  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 28  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 29  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 30  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000002 
MAIN_Cortex_R5_0_0: GEL Output: *******************************

mdio config : phy 1
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 0  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00001140 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 1  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00007949 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 2  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00002000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 3  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x0000A231 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 4  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x000001E1 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 5  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 6  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000064 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 7  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00002001 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 8  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 9  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000300 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 10  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 11  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 12  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 13  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 14  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 15  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00003000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 16  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00005848 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 17  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000302 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 18  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 19  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000044 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 20  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x000029C7 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 21  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 22  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 23  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000040 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 24  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00006150 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 25  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00004444 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 26  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000002 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 27  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 28  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 29  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 30  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000002 
MAIN_Cortex_R5_0_0: GEL Output: *******************************

mdio config : phy 2
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 0  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00001140 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 1  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x0000796D 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 2  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00002000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 3  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x0000A231 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 4  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x000001E1 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 5  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x0000C5E1 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 6  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x0000006D 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 7  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00002001 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 8  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00004006 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 9  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000300 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 10  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00003800 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 11  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 12  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 13  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 14  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 15  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00003000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 16  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00005848 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 17  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x0000AC02 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 18  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 19  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 20  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x000029C7 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 21  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 22  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 23  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000040 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 24  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00006150 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 25  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00004444 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 26  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000002 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 27  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 28  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 29  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000000 
MAIN_Cortex_R5_0_0: GEL Output: *******************************
MAIN_Cortex_R5_0_0: GEL Output: PHY_REG ADDRESS   = 30  
MAIN_Cortex_R5_0_0: GEL Output: PHYREG READ VALUE =  0x00000002 
MAIN_Cortex_R5_0_0: GEL Output: *******************************


ale print table
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: -------CPSW9G ALE TABLE----------------------
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 0 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 300
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 1 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 400
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 2 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 401
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 3 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 402
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 4 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 403
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 5 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 404
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 6 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 405
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 7 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 406
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 8 - VLAN INNER 
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 407
MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 9 - Multicast
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: PORT_MASK        = 0x000001FF
MAIN_Cortex_R5_0_0: GEL Output: SUPER            = 0
MAIN_Cortex_R5_0_0: GEL Output: MCAST IGNORE BITS= 0
MAIN_Cortex_R5_0_0: GEL Output: MCAST_FWD_STATE  = 0
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_0: GEL Output: MULTICAST_ADDR   = 0x0000FFFF 0xFFFFFFFF
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 10 - Unicast
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: TRUNK            = 0
MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER      = 0
MAIN_Cortex_R5_0_0: GEL Output: BLOCK            = 0
MAIN_Cortex_R5_0_0: GEL Output: SECURE           = 1
MAIN_Cortex_R5_0_0: GEL Output: TOUCH            = 0
MAIN_Cortex_R5_0_0: GEL Output: AGEABLE          = 0
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D92C2
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output:  Entry 11 - Unicast
MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_0: GEL Output: TRUNK            = 0
MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER      = 0
MAIN_Cortex_R5_0_0: GEL Output: BLOCK            = 0
MAIN_Cortex_R5_0_0: GEL Output: SECURE           = 0
MAIN_Cortex_R5_0_0: GEL Output: TOUCH            = 0
MAIN_Cortex_R5_0_0: GEL Output: AGEABLE          = 0
MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D92C1


enetctrl cfg
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: ==============================
MAIN_Cortex_R5_0_0: GEL Output:      CPSW2G MAC Mode Config   
MAIN_Cortex_R5_0_0: GEL Output: ==============================
MAIN_Cortex_R5_0_0: GEL Output: Port 0: Mode: RGMII, RGMII-ID:Enabled 
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: ==============================
MAIN_Cortex_R5_0_0: GEL Output:      CPSW9G MAC Mode Config   
MAIN_Cortex_R5_0_0: GEL Output: ==============================
MAIN_Cortex_R5_0_0: GEL Output: Port 0: Mode: RGMII, RGMII-ID:Enabled 
MAIN_Cortex_R5_0_0: GEL Output: Port 1: Mode: RGMII, RGMII-ID:Enabled 
MAIN_Cortex_R5_0_0: GEL Output: Port 2: Mode: RGMII, RGMII-ID:Enabled 
MAIN_Cortex_R5_0_0: GEL Output: Port 3: Mode: RGMII, RGMII-ID:Enabled 
MAIN_Cortex_R5_0_0: GEL Output: Port 4: Mode: SGMII
MAIN_Cortex_R5_0_0: GEL Output: Port 5: Mode: SGMII
MAIN_Cortex_R5_0_0: GEL Output: Port 6: Mode: SGMII
MAIN_Cortex_R5_0_0: GEL Output: Port 7: Mode: SGMII

  • 0
    Prodigy 110 points

    Here are the outputs of the debug scripts.

    Geldebug

  • 0 in reply to Spencer Hill
    TI__Mastermind 37435 points

    Hi Spencer,

    Are you receiving BC frames on Port 0 and Transmitting on Port 7 ? Can you explain the packet flow so I can correlate with stats ?

    Also, are the VID settings intentional ?

    Regards

    Vineet

  • 0
    Prodigy 110 points

    Here are the two bootlogs requested during the debugging session:

    j7-bootlog

    switch-bootlog

  • 0 in reply to Spencer Hill
    TI__Mastermind 37435 points

    Hi Spencer,

    I am closing this ticket since we debugged over a call and followed up offline. The resolution is that Linux core cannot receive Broadcast frames right now due to a limitation and this feature will be support in SDK 8.1 (Nov 2021)

    Regards

    Vineet