Hi HaTa,

You can use k3conf tool in the SDK for checking clock frequencies:
Check the device ID here for all the modules of J7: software-dl.ti.com/.../devices.html

DDR - ID 47: as per the sheet:

k3conf dump clock 47
|--------------------------------------------------------------------------------|
| VERSION INFO |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-34-g1ff0c4f built Thu Nov 19 18:17:32 UTC 2020) |
| SoC | J721E SR1.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0014 '20.8.5--v2020.08b (Terrific Lla)') |
|--------------------------------------------------------------------------------|

|---------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|---------------------------------------------------------------------------------------|
| 47 | 0 | DEV_DDR0_DDRSS_VBUS_CLK | CLK_STATE_READY | 1000000000 |
| 47 | 1 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
| 47 | 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 933000000 |
| 47 | 3 | DEV_DDR0_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 |
| 47 | 4 | DEV_DDR0_DDRSS_IO_CK_N | CLK_STATE_READY | 0 |
| 47 | 5 | DEV_DDR0_DDRSS_IO_CK | CLK_STATE_READY | 0 |
|---------------------------------------------------------------------------------------|

So DDR Frequency will be DEV_DDR0_DDRSS_DDR_PLL_CLK  * 4
i.e 933000000  * 4 = 3,732,000,000

A72 Frequency:

k3conf dump clock 202
|--------------------------------------------------------------------------------|
| VERSION INFO |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-34-g1ff0c4f built Thu Nov 19 18:17:32 UTC 2020) |
| SoC | J721E SR1.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0014 '20.8.5--v2020.08b (Terrific Lla)') |
|--------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|-----------------------------------------------------------------------------------------|
| 202 | 2 | DEV_A72SS0_CORE0_ARM_CLK_CLK | CLK_STATE_READY | 2000000000 |
|-----------------------------------------------------------------------------------------|

R5F Frequency:

k3conf dump clock 245
|--------------------------------------------------------------------------------|
| VERSION INFO |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-34-g1ff0c4f built Thu Nov 19 18:17:32 UTC 2020) |
| SoC | J721E SR1.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0014 '20.8.5--v2020.08b (Terrific Lla)') |
|--------------------------------------------------------------------------------|

|---------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|---------------------------------------------------------------------------------------------|
| 245 | 0 | DEV_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 |
| 245 | 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 |
| 245 | 2 | DEV_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 |
|---------------------------------------------------------------------------------------------|

For changing A72 You can use k3conf as well:

devmem2 0x688040 w 0x80000001

followed by:

k3conf set clock 202 2 1200000000
|--------------------------------------------------------------------------------|
| VERSION INFO |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-34-g1ff0c4f built Thu Nov 19 18:17:32 UTC 2020) |
| SoC | J721E SR1.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0014 '20.8.5--v2020.08b (Terrific Lla)') |
|--------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|-----------------------------------------------------------------------------------------|
| 202 | 2 | DEV_A72SS0_CORE0_ARM_CLK_CLK | CLK_STATE_READY | 1200000000 |
|-----------------------------------------------------------------------------------------|

For changing R5F frequency:

 k3conf set clock 245 0 500000000
|---------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|---------------------------------------------------------------------------------------------|
| 245 | 0 | DEV_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 500000000 |
| 245 | 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 500000000 |
| 245 | 2 | DEV_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 500000000 |

For DDR frequency updating you will need to change k3-j721e-ddr-evm-lp4-3733.dtsi corresponding to
the speed you need. This is more involved and not straight forward.

Note: You can not change all the frequencies using k3conf.

Best Regards,
Keerthy