DM3730 DVSDK release for 200 MHz SDRAM

Hi Orjan,

I am not sure about DVSDK release versioning, but if you have Hynix memory part with AM/DM37x device then I believe the default x-loader/u-boot and kernel from PSP03.00.01.06 release (X-loader - 1.46 UBoot - 2009.11 kernel - 2.6.32).

To check kernel version you can use "cat /proc/ti-psp-version"

Thanks,

Vaibhav

Hi Vaibhav,

I use TI_Android_FroYo_DevKit-V2(with u-boot-03.00.02.07) & also compare with UBoot - 2009.11 code.

There is no code related to change L3/SDRC clock to 200Mhz. My board is still 165Mhz.

The code belows is only change the DDR setting for Hynix part of AM/DM37xEVM (200MHz optimized), but the L3 clock is still as old one.

if (is_cpu_family(CPU_OMAP36XX)) {

writel(V_ACTIMA_200, &sdrc_actim_base->ctrla);

writel(V_ACTIMB_200, &sdrc_actim_base->ctrlb);

} else {

writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);

writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);

}

Thanks,

Allen

Allen,

Please note that, u-boot doesn't configure SDRC settings, since the time u-boot comes up you are already running from DDR. X-Loader is the one who configures it and load the u-boot. So you should look for x-loader for SDRC settings.

Try using u-boot from Arago -

X-loader - http://arago-project.org/git/projects/?p=x-load-omap3.git;a=shortlog;h=refs/heads/OMAPPSP_03.00.01.06

U-boot - http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=shortlog;h=refs/heads/OMAPPSP_03.00.01.06

Thanks,

Vaibhav

Hi Vaibhav,

I had checkout the x-loader(psp 3.00.01.06) code from arago git.

The L3 define(mem.h) is still for 166Mhz (#  define CORE_L3_DIV    2        /* 166MHz : L3 {DDR} */).

Do I miss something? There is only one CORE_L3_DIV.

Thanks,

Allen

Allen

You are missing code implementation in mem.c file -

        if (is_cpu_family() == CPU_OMAP36XX) {
                if (is_ddr_166M) {
                        __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
                        __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
                } else {
                        __raw_writel(HYNIX_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
                        __raw_writel(HYNIX_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
                }
        } else {

The values defined in mem.h file as

#define HYNIX_SDRC_ACTIM_CTRLA_0        HYNIX_V_ACTIMA_200
#define HYNIX_SDRC_ACTIM_CTRLB_0        HYNIX_V_ACTIMB_200

This is all for SDRC configuration. As far as L3 clock configuration is concerned, look at prcm_init function is omap3evm.c file. Also please note that, we are detecting whether the device is 166MHz or 200MHz is based on NAND ID detection. It the NAND part if Micron we choose 166MHz and for hynix it would be 200MHz, default being 166MHz. Follow variable "is_ddr_166M" in omap3evm.c and k9f1g08r0a.c file,

Thanks,

Vaibhav