DRA821U: FPGA communication via SPI module

Part Number: DRA821U

Hi,

I want to connect the CPU to FPGA via SPI link and do the following:

1. write 32 bit data to 32 bit address space (it's 64 bits master write(address and data))

2. read 32 bit data from 32 bit address space (it's 32 bits master write(address) and 32 bits master read(data))

3. control the time which the master waiting for the data in the read cycle by the slave

This activity is done in our current CPU via local bus contain data bus, address bus, Chip_select,write, out_enable, Transfer_ack...

pls. advise who is the best way to do it via the SPI.

Regards

Zeev Gerber