• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 2 answers
  • Subscribers 98 subscribers
  • Views 232 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AM3352: Inquiry about Build-warnings of Processor SDK Linux 06_03_00_106

AM3352: Inquiries about DDR3(4GB) implementation

Takayuki Miyazaki
Genius 10120 points
Part Number: AM3352

Hi team,

Customer was developing their system with AM3352BZCZ60/DDR3(128Mb×16 SDRAM: 2GB), however, Since customer has not been able to gain this DDR3(2GB) suddenly because of the discontinued , customer plans to use other DDR3(4GB) in a hurry. Regarding memory-size(memory-map), customer will use this DDR3(4GB) as DDR3(2GB).  For this system, it seems customer connected DDR_A14/ DDR_A15 to DDR3(4GB). Therefore, customer is asking the following inquires.

Customer sets “reg_rowsize” (in SDRAM_CONFIG Register) to “5h”. it means “(14 row bits = DDR_A0-A13 )”. The detail register configuration is attached (AM3352_SRAM_CONFIG_REGISTER.zip). In this case,

1. For DDR_A14 and DDR_A15 terminals, are those terminals outputting “High” ? I mean, According “Table 4-1 Pin Attributes” in datasheet,  DDR_A14 and DDR_A15 pins shows “H” on “BALL RESET REL STATE”. This means, customer understand those pins drives VOH. Is that correct?

2. It TI has any concerns about this DDR3(4G) implementation. Could you share them, please?

It will be really appreciated if you will share your Expert’s comments on this quickly, because customer need to fix their schematic as soon as possible.

Best regards,

Miyazaki

  • 0
    TI__Guru* 86820 points

    Miyazaki, i'm a little confused at what the customer board has connected.  If the customer designed the board for a 128Mx16 (which is a 2Gbit memory), then at the very least they need to connect A[13:0].  You said they also connected A14 and A15 to the memory, so in reality, they could support up to an 8Gbit memory.  If they choose to only use 2Gbit of the 4Gbit memory, then A14 and A15 state can be controlled using internal pull up/down resistors configured in the ddr_cmdX_ioctrl registers.  Although, i don't think they should need to worry about this, as the memory will work with these signals in either state

    Ensure that they use the AM335x DDR configuration tool (spreadsheet link is in app note): https://www.ti.com/lit/pdf/sprack4  This will configure the complete DDR subsystem

    Regards,

    james

  • 0 in reply to JJD
    TI__Genius 10120 points

    Hello james,

    Thank you for always helping me and I’m sorry to confuse you… I just translated them. In case of using DDR3(4G), I think A14 also is used, however, A15 is not used. I shared your comments with customer. I’d like to wait their feedback for a while.

    Best regards,

    Miyazaki