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VPBE pixel clock for LCD - Question about PLL manipulation and clk src to get the right clk for LCD

DJH
Intellectual 985 points

I need a little direction to understand the clock situation for the VPBE system - I am using the DM365 216MHz and I am currently placing a 24MHz crystal for MXI.  I need an external pixel clk (or dot clk, pclk, ...) of no more than 15MHz for my 128x160 1.8" RGB display.  Table 3.6 of the DM365 datasheet is confusing to me and seems to indicate that the VENC requires 27MHz (which it gets by dividing the PLL2 clock by 16).

If I look at fig 38 of sprufg9c, it looks like VENC clk goes right into the LCD controller - but I don't want 27MHz out for the pixel clock.  Section 4.5.4.4 of that same document  says that dotclock (pixel clock for me, i've hooked to vclk) can be programmed, but goes on to talk more about waveform shaping and level adjusting.  It concludes showing how dotclk is sourced from the VENC clk.

 

Figure 5 in sprufg5a shows how VENC clk can be sourced from several locations: one each from the PLL's, the crystal directly, and from an external clk pad.  (and pclk - but that's on the VPFE and I take that to be the pclk coming in from the image sensor.)  This document shows where the clk dividers are and each peripheral associated with the PLL's.

So my questions are these:

1.  Can I get an appropriate clk for the LCD from one of these internal sources, and map it out to VCLK?  I need anything from about 1MHz to 15MHz.

2.  Will that affect the other peripherals?

Thank you!

-David

  • 0
    Prodigy 160 points

    Hi David,

    I did the following to generate a low pixel clock frequency ( < 8 MHz) for my LCD.

    - Use PLL1 SYSCLK6 as the source for the VENC clock, programmed to give 27 MHz

    - Programmed registers DCLKCTL and DCLKPTN0-3 registers to divide the 27 MHz clock, down to the required frequency for the LCD pixel clock

    - Programmed registers OSDCLK0 and OSDCLK1 to divide the OSD module clock by the same factor

    In your case it may be enough to just program a larger divider value for PLL1 SYSCLK6 to give you a frequency less than 15 MHz, but for me that was not enough as I needed a pixel clock less than 8 MHz.

    Stathis