DM37x Suspend/Resume and SYS_OFF_MODE

The PRCM register dump helps to identify the issue. Do you now when in the suspend/resume sequence it's taken ? Can you take the same register snapshot just before ARM executes WFI to go into the suspend ?

It seems indeed that you still have a lot of clocks on before going to suspend. To get a more accurate snapshot, edit WINCE600\PLATFORM\COMMON\src\soc\COMMON_TI_V1\OMAP3530\OAL\PRCM\prcm.c

and change the following:

#ifndef

if (g_PrcmDebugSuspendResume)

{

OALWakeupLatency_SaveSnapshot();

PrcmSaveRefCounts();

PrcmRegsSnapshot();

}

#endif

PrcmDeviceEnableClocksKernel(OMAP_DEVICE_OMAPCTRL, FALSE);

PrcmRegsSnapshot();

// Move SoC/CPU to idle mode (suspend)

fnOALCPUIdle(g_pCPUInfo);

Below is an update, with the snapshot taken at the revised spot per the Adeneo post, namely immediately before the fnOALCPUIdle.  The snapshot is printed only after the resume.  I also include the PM_PREPWSTST_XXX registers read AFTER the resume, at the bottom. This shows that several modules that did not go OFF. One concern I have is with the IVA2 pending wakeup (PRM_IRQSTATUS_IVA2 = 0x02); I cannot seem to clear that bit before going to CPU Idle, yet the manual says if IRQSTATUS bits are not cleared, then it may prevent a domain from going to Idle. We are not using IVA2, and per the pre-suspend snapshot, the clocks are not even enabled.

To Adeneo Support: We are using your BSP, which module(s) should be turning off the clocks? Although this output is a rebuild of your BSP for our platform, we saw the same issue with stock build running on the 3730 EVM, in which the only change made was enabling the printing of the snapshot registers after the resume. If there is a specific version of your BSP that correctly turns off all clocks and goes to OFF mode, and prints the registers from the snapshot, then please point me to that binary, so that I can try it and confirm.

Before the PrcmDeviceEnableClocksKernel() call, I also tried adding the following sequence of commands to force disable IVA2, but it did not seem to make a difference.

    OUTREG32(&g_pPrcmPrm->pOMAP_IVA2_PRM->PRM_IRQSTATUS_IVA2, 7);
    OUTREG32(&g_pPrcmCm->pOMAP_IVA2_CM->CM_CLKSEL2_PLL_IVA2,0);
    OUTREG32(&g_pPrcmPrm->pOMAP_IVA2_PRM->PM_WKDEP_IVA2,0);
    OUTREG32(&g_pPrcmCm->pOMAP_IVA2_CM->CM_FCLKEN_IVA2,0);
    OUTREG32(&g_pPrcmCm->pOMAP_IVA2_CM->CM_CLKEN_PLL_IVA2,0);
    OUTREG32(&g_pPrcmPrm->pOMAP_IVA2_PRM->PM_PWSTCTRL_IVA2,0x30107);
    OUTREG32(&g_pPrcmCm->pOMAP_IVA2_CM->CM_CLKSTCTRL_IVA2,2);
    OUTREG32(&g_pPrcmPrm->pOMAP_IVA2_PRM->PM_PWSTCTRL_IVA2,0x30104);
    OUTREG32(&g_pPrcmCm->pOMAP_IVA2_CM->CM_CLKSTCTRL_IVA2,1);

The register snapshot taken before the fnOALCPUIdle() call is the following:

IVA2_CM:
  CM_FCLKEN_IVA2           0x00000000
  CM_CLKEN_PLL_IVA2        0x00000001
  CM_IDLEST_IVA2           0x00000001
  CM_IDLEST_PLL_IVA2       0x00000001
  CM_AUTOIDLE_PLL_IVA2     0x00000000
  CM_CLKSEL1_PLL_IVA2      0x00114a0c
  CM_CLKSEL2_PLL_IVA2      0x00000001
  CM_CLKSTCTRL_IVA2        0x00000001
  CM_CLKSTST_IVA2          0x00000001

OCP_System_Reg_CM:
  CM_REVISION              0x00000010
  CM_SYSCONFIG             0x00000001

MPU_CM:
  CM_CLKEN_PLL_MPU         0x0000027f
  CM_IDLEST_MPU            0x00000000
  CM_IDLEST_PLL_MPU        0x00000001
  CM_AUTOIDLE_PLL_MPU      0x00000001
  CM_CLKSEL1_PLL_MPU       0x0011900c
  CM_CLKSEL2_PLL_MPU       0x00000001
  CM_CLKSTCTRL_MPU         0x00000003
  CM_CLKSTST_MPU           0x00000001

CORE_CM:
  CM_FCLKEN1_CORE          0x00000000
  CM_FCLKEN3_CORE          0x00000000
  CM_ICLKEN1_CORE          0x00000002
  CM_ICLKEN2_CORE          0x00000000
  CM_ICLKEN3_CORE          0x00000000
  CM_IDLEST1_CORE          0xfffffffd
  CM_IDLEST2_CORE          0x0000001f
  CM_IDLEST3_CORE          0x0000000d
  CM_AUTOIDLE1_CORE        0x00000000
  CM_AUTOIDLE2_CORE        0x00000000
  CM_AUTOIDLE3_CORE        0x00000000
  CM_CLKSEL_CORE           0x0000130a
  CM_CLKSTCTRL_CORE        0x0000003f
  CM_CLKSTST_CORE          0x00000003

SGX_CM:
  CM_FCLKEN_SGX            0x00000000
  CM_ICLKEN_SGX            0x00000000
  CM_IDLEST_SGX            0x00000001
  CM_CLKSEL_SGX            0x00000000
  CM_SLEEPDEP_SGX          0x00000000
  CM_CLKSTCTRL_SGX         0x00000003
  CM_CLKSTST_SGX           0x00000000

WKUP_CM:
  CM_FCLKEN_WKUP           0x00000008
  CM_ICLKEN_WKUP           0x0000000c
  CM_IDLEST_WKUP           0x000002f3
  CM_AUTOIDLE_WKUP         0x00000000
  CM_CLKSEL_WKUP           0x00000014

Clock_Control_Reg_CM:
  CM_CLKEN_PLL             0x007f000f
  CM_CLKEN2_PLL            0x0000000f
  CM_IDLEST_CKGEN          0x00000001
  CM_IDLEST2_CKGEN         0x00000000
  CM_AUTOIDLE_PLL          0x00000009
  CM_AUTOIDLE2_PLL         0x00000001
  CM_CLKSEL1_PLL           0x08c80c00
  CM_CLKSEL2_PLL           0x0483600c
  CM_CLKSEL3_PLL           0x00000009
  CM_CLKSEL4_PLL           0x0000780c
  CM_CLKSEL5_PLL           0x00000001
  CM_CLKOUT_CTRL           0x00000003

DSS_CM:
  CM_FCLKEN_DSS            0x00000000
  CM_ICLKEN_DSS            0x00000000
  CM_IDLEST_DSS            0x00000002
  CM_AUTOIDLE_DSS          0x00000000
  CM_CLKSEL_DSS            0x00001009
  CM_SLEEPDEP_DSS          0x00000000
  CM_CLKSTCTRL_DSS         0x00000003
  CM_CLKSTST_DSS           0x00000001

CAM_CM:
  CM_FCLKEN_CAM            0x00000000
  CM_ICLKEN_CAM            0x00000000
  CM_IDLEST_CAM            0x00000001
  CM_AUTOIDLE_CAM          0x00000000
  CM_CLKSEL_CAM            0x00000004
  CM_SLEEPDEP_CAM          0x00000000
  CM_CLKSTCTRL_CAM         0x00000003
  CM_CLKSTST_CAM           0x00000000

PER_CM:
  CM_FCLKEN_PER            0x00000000
  CM_ICLKEN_PER            0x00000000
  CM_IDLEST_PER            0x0007ffff
  CM_AUTOIDLE_PER          0x00000000
  CM_CLKSEL_PER            0x00000001
  CM_SLEEPDEP_PER          0x00000002
  CM_CLKSTCTRL_PER         0x00000003
  CM_CLKSTST_PER           0x00000001

EMU_CM:
  CM_CLKSEL1_EMU           0x03020a50
  CM_CLKSTCTRL_EMU         0x00000003
  CM_CLKSTST_EMU           0x00000000
  CM_CLKSEL2_EMU           0x00000000
  CM_CLKSEL3_EMU           0x00000000

Global_Reg_CM:
  CM_POLCTRL               0x00000000

NEON_CM:
  CM_IDLEST_NEON           0x00000000
  CM_CLKSTCTRL_NEON        0x00000003

USBHOST_CM:
  CM_FCLKEN_USBHOST        0x00000000
  CM_ICLKEN_USBHOST        0x00000000
  CM_IDLEST_USBHOST        0x00000003
  CM_AUTOIDLE_USBHOST      0x00000000
  CM_SLEEPDEP_USBHOST      0x00000000
  CM_CLKSTCTRL_USBHOST     0x00000003
  CM_CLKSTST_USBHOST       0x00000000

IVA2_PRM:
  RM_RSTCTRL_IVA2          0x00000007
  RM_RSTST_IVA2            0x00000000
  PM_WKDEP_IVA2            0x00000000
  PM_PWSTCTRL_IVA2         0x00cf0104
  PM_PWSTST_IVA2           0x00000ff7
  PM_PREPWSTST_IVA2        0x00000ff7
  PRM_IRQSTATUS_IVA2       0x00000002
  PRM_IRQENABLE_IVA2       0x00000000

OCP_System_Reg_PRM:
  PRM_REVISION             0x00000010
  PRM_SYSCONFIG            0x00000001
  PRM_IRQSTATUS_MPU        0x00000010
  PRM_IRQENABLE_MPU        0x01c926a0

MPU_PRM:
  RM_RSTST_MPU             0x00000000
  PM_WKDEP_MPU             0x00000000
  PM_EVGENCTRL_MPU         0x00000012
  PM_EVGENONTIM_MPU        0x00000000
  PM_EVGENOFFTIM_MPU       0x00000000
  PM_PWSTCTRL_MPU          0x00030104
  PM_PWSTST_MPU            0x000000c7
  PM_PREPWSTST_MPU         0x000000c7

CORE_PRM:
  RM_RSTST_CORE            0x00000000
  PM_WKEN1_CORE            0x00000000
  PM_MPUGRPSEL1_CORE       0xc33ffe18
  PM_IVA2GRPSEL1_CORE      0xc33ffe18
  PM_WKST1_CORE            0x00000000
  PM_WKST3_CORE            0x00000000
  PM_PWSTCTRL_CORE         0x000f0300
  PM_PWSTST_CORE           0x000000f7
  PM_PREPWSTST_CORE        0x000000f7
  PM_WKEN3_CORE            0x00000004
  PM_IVA2GRPSEL3_CORE      0x00000004
  PM_MPUGRPSEL3_CORE       0x00000004

SGX_PRM:
  RM_RSTST_SGX             0x00000000
  PM_WKDEP_SGX             0x00000000
  PM_PWSTCTRL_SGX          0x00030104
  PM_PWSTST_SGX            0x00000000
  PM_PREPWSTST_SGX         0x00000000

WKUP_PRM:
  PM_WKEN_WKUP             0x0000010a
  PM_MPUGRPSEL_WKUP        0x000003cb
  PM_IVA2GRPSEL_WKUP       0x00000000
  PM_WKST_WKUP             0x00000000

Clock_Control_Reg_PRM:
  PRM_CLKSEL               0x00000003
  PRM_CLKOUT_CTRL          0x00000080

DSS_PRM:
  RM_RSTST_DSS             0x00000004
  PM_WKEN_DSS              0x00000000
  PM_WKDEP_DSS             0x00000000
  PM_PWSTCTRL_DSS          0x00030104
  PM_PWSTST_DSS            0x00000003
  PM_PREPWSTST_DSS         0x00000003

CAM_PRM:
  RM_RSTST_CAM             0x00000000
  PM_WKDEP_CAM             0x00000000
  PM_PWSTCTRL_CAM          0x00030104
  PM_PWSTST_CAM            0x00000000
  PM_PREPWSTST_CAM         0x00000000

PER_PRM:
  RM_RSTST_PER             0x00000000
  PM_WKEN_PER              0x0003e000
  PM_MPUGRPSEL_PER         0x0003efff
  PM_IVA2GRPSEL_PER        0x0007efff
  PM_WKST_PER              0x00000000
  PM_WKDEP_PER             0x00000012
  PM_PWSTCTRL_PER          0x00030104
  PM_PWSTST_PER            0x00000007
  PM_PREPWSTST_PER         0x00000007

EMU_PRM:
  RM_RSTST_EMU             0x00000000
  PM_PWSTST_EMU            0x00000000

Global_Reg_PRM:
  PRM_VC_SMPS_SA           0x00000000
  PRM_VC_SMPS_VOL_RA       0x00000000
  PRM_VC_SMPS_CMD_RA       0x00000000
  PRM_VC_CMD_VAL_0         0x00000000
  PRM_VC_CMD_VAL_1         0x00000000
  PRM_VC_CH_CONF           0x00000000
  PRM_VC_I2C_CFG           0x00000018
  PRM_VC_BYPASS_VAL        0x00000000
  PRM_RSTCTRL              0x00000000
  PRM_RSTTIME              0x00001006
  PRM_RSTST                0x00000000
  PRM_VOLTCTRL             0x0000000c
  PRM_SRAM_PCHARGE         0x00000050
  PRM_CLKSRC_CTRL          0x00000091
  PRM_OBS                  0x00000000
  PRM_VOLTSETUP1           0x01120112
  PRM_VOLTOFFSET           0x00000000
  PRM_CLKSETUP             0x000000a0
  PRM_POLCTRL              0x00000002
  PRM_VOLTSETUP2           0x00000000

NEON_PRM:
  RM_RSTST_NEON            0x00000000
  PM_WKDEP_NEON            0x00000002
  PM_PWSTCTRL_NEON         0x00000004
  PM_PWSTST_NEON           0x00000003
  PM_PREPWSTST_NEON        0x00000003

USBHOST_PRM:
  RM_RSTST_USBHOST         0x00000000
  PM_WKEN_USBHOST          0x00000000
  PM_MPUGRPSEL_USBHOST     0x00000001
  PM_IVA2GRPSEL_USBHOST    0x00000001
  PM_WKST_USBHOST          0x00000000
  PM_WKDEP_USBHOST         0x00000000
  PM_PWSTCTRL_USBHOST      0x00030104
  PM_PWSTST_USBHOST        0x00000000
  PM_PREPWSTST_USBHOST     0x00000000

The PM_PREPWSTST_XXX registers AFTER resuming are the following:

  PM_PREPWSTST_IVA2        0x00000ff7
  PM_PREPWSTST_MPU         0x00000000
  PM_PREPWSTST_CORE        0x000000f7
  PM_PREPWSTST_SGX         0x00000000
  PM_PREPWSTST_DSS         0x00000003
  PM_PREPWSTST_CAM         0x00000000
  PM_PREPWSTST_PER         0x00000000
  PM_PREPWSTST_NEON        0x00000000
  PM_PREPWSTST_USBHOST     0x00000000

As you can see, only IVA2, CORE, and DSS remain on. Advice on how (and where) to turn those off would be appreciated.

Thanks,
Dave