J721EXCPXEVM: DDR4 configuration in SBL

Hi,

I would like to confirm DDR configuration of SBL on j721e evm board.

Is my understanding is correct ?

<1> DDR clock is 1.0665 GHz

ti-processor-sdk-rtos-j721e-evm-07_02_00_06\pdk_jacinto_07_01_05_14\packages\ti\board\src\j721e_evm\include
board_ddrRegInit.h

#define DDRSS_PLL_FREQUENCY_1 1066500000


ti-processor-sdk-rtos-j721e-evm-07_02_00_06\pdk_jacinto_07_01_05_14\packages\ti\board\src\j721e_evm
board_ddr.c

static Board_STATUS Board_DDRSetPLLClock(void)
{
    Board_STATUS status = BOARD_SOK;

    status = Board_PLLInit(TISCI_DEV_DDR0,
                           TISCI_DEV_DDR0_DDRSS_DDR_PLL_CLK,
                           DDRSS_PLL_FREQUENCY_1);
    if(status != BOARD_SOK)
    {
        BOARD_DEBUG_LOG("Failed to Set the DDR PLL Clock Frequency\n");
    }

    return status;
}

<2> DDR init area is addr: 0x8000 0000  size: 0x8000 0000(2GB)

No init for addr: 0x8 8000 0000  size: 0x8000 0000(2GB) 

ti-processor-sdk-rtos-j721e-evm-07_02_00_06\pdk_jacinto_07_01_05_14\packages\ti\boot\sbl\board\k3
sbl_main.c

const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
    ...
    
    {
        /* Region 4 configuration: 2 GB DDR RAM */
        .regionId         = 4U,
        .enable           = 1U,
        .baseAddr         = 0x80000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
        .memAttr          = 0U,
    },

Best Regards, 

Seiki Tatesawa