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AM5728: Unable to print early boot in uboot for am5728

Jigar Patel
Prodigy 10 points
Part Number: AM5728
Other Parts Discussed in Thread: BEAGLEBOARD-X15

Hello,

I'm using processor sdk 5.02 with am5728.I'm trying to port uboot 2018.01 to our Custom designed board based on AM5728 EVM board.

So i've modified our ram timing as described in AM57x, DRA7x, and TDA2x EMIF Tools.pdf and updated uboot files according, Default uart is on the same port as beagleboard evm.Modified other pinmux configuration as per requirement.But still board doesn't start so trying to enable early debug print in spl so i've modified uboot as per below.

Added below line in include/configs/am57xx_evm.h

#define DEBUG 1

Updated uboot config to this and modified default uboot config file in configs/am57xx_evm_defconfig

CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_OMAP=y
CONFIG_DEBUG_UART_BASE=0x48020000
CONFIG_DEBUG_UART_CLOCK=48000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y

Still i'm not getting any output on serial.

While trying to debug using XDS110 it stuck at below line in file drivers/serial/ns16550.c

static inline void _debug_uart_putc(int ch)
{
	struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;

-->	while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
		;
	serial_dout(&com_port->thr, ch);
}

While debugging uboot sometimes it jumps to 0xc mmc_fat_write funtion and the reason is not always the same line.

Can anybody guide me how to troubleshoot this issue.

Thanks,

  • 0
    TI__Guru**** 163660 points

    Hi Jigar,

    I believe the intent here is to bring up your custom board. If you already have XDS then you need not have debug prints
    and go on debugging with the debugger itself correct? Without debug enabled where exactly are you stuck when
    you attach xds?

    Also can you consider moving to latest 6.03 SDK: software-dl.ti.com/.../index_FDS.html

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 10 points

    I've modified uboot 2019.01 from processor sdk 6.03 but still same issue.

    Modified GEL files as per below -

    IS_EMIF2_AVAILABLE to 0

    MEMMAP_2GB_INTL_EMIFX2 to 0

    MEMMAP_2GB_NON_INTL_EMIFX2 to 1

    We have two revision of custom designed boards.

    We are using USB1 for msc device.

    We have a problem in R0 with VDDA_USB2 tied to GND so to resolve that bug created a revision and connected VDDA_USB2 to VDDA_USB1 which is connected to 1.8V PHY as shown in Beagleboard-X15 schematics.

    R0 works with GEL file from ccs directory on above defined changes and completes HW levelling of DDR RAM.

    while R1 fails with ERROR: HW-Leveling time-out for same GEL file while creating comparison for PRCM_Get_Config from GEL files below are the changes observed.

    R0

    CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================

    R1

    CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================

    How to troubleshoot further.

    Here i've attached my GEL file output log for both working and not working.

    Working GEL

    Fullscreen WORKING_GEL_LOG.txt Download 
    CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Two EMIFs in non interleaved mode (2GB total)
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---


CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 0: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 1: 0x00000078
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 2: 0x0000007D
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 3: 0x0000007A
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 4: 0x00000000
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 0: 0x00000043
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 1: 0x0000003E
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 2: 0x0000003E
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 3: 0x00000039
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 4: 0x0000007F
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 0: 0x00000068
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 1: 0x00000065
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 2: 0x0000006A
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 3: 0x0000006B
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 4: 0x00000073
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 0: 0x00000048
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 1: 0x00000045
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 2: 0x0000004A
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 3: 0x0000004B
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 4: 0x00000053
CortexA15_0: GEL Output: 


CortexA15_0: GEL Output: -------------------------------------------------------
CortexA15_0: GEL Output:  PRCM State of all modules on the device
CortexA15_0: GEL Output: -------------------------------------------------------
CortexA15_0: GEL Output: Module : DMA_SYSTEM (CD_DMA, PD_CORE)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSP1 (CD_DSP1, PD_DSP1)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSP2 (CD_DSP2, PD_DSP2)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : BB2D (CD_DSS, PD_DSS)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSS (CD_DSS, PD_DSS)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DLL (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DMM (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF1 (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF2 (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF_OCP_FW (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CPGMAC (CD_GMAC, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPU (CD_GPU, PD_GPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : OFF
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C5 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP1 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER5 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER6 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER7 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER8 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART6 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IPU1 (CD_IPU1, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IPU2 (CD_IPU2, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IVA (CD_IVA, PD_IVA)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SL2 (CD_IVA, PD_IVA)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IEEE1500_2_OCP (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC2 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SATA (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS2 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS4 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CTRL_MODULE_BANDGAP (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DLL_AGING (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_INSTR (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_MAIN_2 (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP_WP_NOC (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPMC (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_MAIN_1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMU_EDMA (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMU_PCIESS (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM2 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM3 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPCC (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPTC1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPTC2 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_CFG (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP2 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SAR_ROM (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SPINLOCK (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IO_DELAY_BLOCK (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX1 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX10 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX11 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX12 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX13 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX2 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX3 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX4 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX5 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX6 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX7 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX8 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX9 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER10 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER11 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER9 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : ELM (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : HDQ1W (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART5 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO5 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO6 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO7 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO8 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DCAN2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART7 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART8 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART9 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PRUSS1 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PRUSS2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP3 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP4 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP5 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP6 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP7 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP8 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS1 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS3 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : QSPI (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER3 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER13 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER14 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER15 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER16 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : AES1 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : AES2 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DES3DES (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : RNG (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SHA2MD51 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SHA2MD52 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU (CD_MPU, PD_MPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU_MPU_DBG (CD_MPU, PD_MPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PCIESS1 (CD_PCIE, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PCIESS2 (CD_PCIE, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : RTCSS (CD_RTC, PD_RTC)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP1 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP2 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP3 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VPE (CD_VPE, PD_VPE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DEBUG_LOGIC (CD_EMU, PD_EMU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU_EMU_DBG (CD_EMU, PD_EMU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : COUNTER_32K (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CTRL_MODULE_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DCAN1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IO_SRCOMP_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : KBD (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SAR_RAM (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER12 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART10 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : WD_TIMER2 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================

    Not Working GEL

    Fullscreen NOT_WORKING_GEL_LOG.txt Download 
    CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output: ERROR: HW-Leveling time-out
CortexA15_0: GEL Output:        Two EMIFs in non interleaved mode (2GB total)
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 0: 0x00000000
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 1: 0x00000000
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 2: 0x00000000
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 3: 0x00000000
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 4: 0x00000000
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 0: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 1: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 2: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 3: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 4: 0x0000007F
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 0: 0x00000077
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 1: 0x00000077
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 2: 0x00000077
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 3: 0x00000077
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 4: 0x00000077
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 0: 0x00000057
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 1: 0x00000057
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 2: 0x00000057
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 3: 0x00000057
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 4: 0x00000057
CortexA15_0: GEL Output: 

CortexA15_0: GEL Output: -------------------------------------------------------
CortexA15_0: GEL Output:  PRCM State of all modules on the device
CortexA15_0: GEL Output: -------------------------------------------------------
CortexA15_0: GEL Output: Module : DMA_SYSTEM (CD_DMA, PD_CORE)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSP1 (CD_DSP1, PD_DSP1)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSP2 (CD_DSP2, PD_DSP2)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : BB2D (CD_DSS, PD_DSS)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSS (CD_DSS, PD_DSS)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DLL (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DMM (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF1 (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF2 (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF_OCP_FW (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CPGMAC (CD_GMAC, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPU (CD_GPU, PD_GPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : OFF
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C5 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP1 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER5 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER6 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER7 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER8 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART6 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IPU1 (CD_IPU1, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IPU2 (CD_IPU2, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IVA (CD_IVA, PD_IVA)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SL2 (CD_IVA, PD_IVA)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IEEE1500_2_OCP (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC2 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SATA (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS2 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS4 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CTRL_MODULE_BANDGAP (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DLL_AGING (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_INSTR (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_MAIN_2 (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP_WP_NOC (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPMC (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_MAIN_1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMU_EDMA (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMU_PCIESS (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM2 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM3 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPCC (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPTC1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPTC2 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_CFG (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP2 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SAR_ROM (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SPINLOCK (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IO_DELAY_BLOCK (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX1 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX10 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX11 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX12 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX13 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX2 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX3 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX4 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX5 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX6 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX7 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX8 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX9 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER10 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER11 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER9 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : ELM (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : HDQ1W (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART5 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO5 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO6 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO7 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO8 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DCAN2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART7 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART8 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART9 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PRUSS1 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PRUSS2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP3 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP4 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP5 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP6 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP7 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP8 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS1 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS3 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : QSPI (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER3 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER13 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER14 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER15 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER16 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : AES1 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : AES2 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DES3DES (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : RNG (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SHA2MD51 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SHA2MD52 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU (CD_MPU, PD_MPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU_MPU_DBG (CD_MPU, PD_MPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PCIESS1 (CD_PCIE, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PCIESS2 (CD_PCIE, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : RTCSS (CD_RTC, PD_RTC)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP1 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP2 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP3 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VPE (CD_VPE, PD_VPE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DEBUG_LOGIC (CD_EMU, PD_EMU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU_EMU_DBG (CD_EMU, PD_EMU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : COUNTER_32K (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CTRL_MODULE_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DCAN1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IO_SRCOMP_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : KBD (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SAR_RAM (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER12 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART10 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : WD_TIMER2 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================

  • 0 in reply to Keerthy J
    Prodigy 10 points

    Hello Keerthy,

    I've tries to port the uboot 2019 provided in processor SDK 6.03 nut still the same issue.

    I have two revision for the same configuration.

    I have modified AM572x_ddr_config.gel file as per below.

    #define HW_LEVELING_ENABLED (1U)
#define IS_EMIF2_AVAILABLE (0U)
#define ENABLE_ECC (0U)
#define MEMMAP_2GB_NON_INTL_EMIFX2 (1U)
#define MEMMAP_2GB_INTL_EMIFX2 (0U)

    While running gpevm_am572x.gel file on both revisions i 've observed some changes due might be to that DDR HW levelling failing.

    Revision R0 DDR RAM HW levelling Passed with default DDR PHY values
    Revision R1 DDR RAM HW levelling Failed and shows "ERROR: HW-Leveling time-out"
    While running AM572X_PRCM_Get_Config.gel i'm getting difference in some modules.

    R0 (Working)

    CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: Module State : ON
CortexA15_0: GEL Output: Clock State : ON
CortexA15_0: GEL Output: Power State : ON
CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: Module State : DISABLED
CortexA15_0: GEL Output: Clock State : ON
CortexA15_0: GEL Output: Power State : ON
CortexA15_0: GEL Output: Final State : MODULE DISABLED
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: Module State : ON
CortexA15_0: GEL Output: Clock State : ON
CortexA15_0: GEL Output: Power State : ON
CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED
CortexA15_0: GEL Output: ==========================================


    R1 (Not Working)

    CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: Module State : DISABLED
CortexA15_0: GEL Output: Clock State : OFF
CortexA15_0: GEL Output: Power State : ON
CortexA15_0: GEL Output: Final State : MODULE DISABLED
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: Module State : DISABLED
CortexA15_0: GEL Output: Clock State : OFF
CortexA15_0: GEL Output: Power State : ON
CortexA15_0: GEL Output: Final State : MODULE DISABLED
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: Module State : DISABLED
CortexA15_0: GEL Output: Clock State : ON
CortexA15_0: GEL Output: Power State : ON
CortexA15_0: GEL Output: Final State : MODULE DISABLED
CortexA15_0: GEL Output: ==========================================


    Here i've attached both the files.
    Please take a look and let me know.

    Thanks,

    Fullscreen 3582.WORKING_GEL_LOG.txt Download 
    CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Two EMIFs in non interleaved mode (2GB total)
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---


CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 0: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 1: 0x00000078
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 2: 0x0000007D
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 3: 0x0000007A
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 4: 0x00000000
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 0: 0x00000043
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 1: 0x0000003E
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 2: 0x0000003E
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 3: 0x00000039
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 4: 0x0000007F
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 0: 0x00000068
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 1: 0x00000065
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 2: 0x0000006A
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 3: 0x0000006B
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 4: 0x00000073
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 0: 0x00000048
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 1: 0x00000045
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 2: 0x0000004A
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 3: 0x0000004B
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 4: 0x00000053
CortexA15_0: GEL Output: 


CortexA15_0: GEL Output: -------------------------------------------------------
CortexA15_0: GEL Output:  PRCM State of all modules on the device
CortexA15_0: GEL Output: -------------------------------------------------------
CortexA15_0: GEL Output: Module : DMA_SYSTEM (CD_DMA, PD_CORE)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSP1 (CD_DSP1, PD_DSP1)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSP2 (CD_DSP2, PD_DSP2)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : BB2D (CD_DSS, PD_DSS)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSS (CD_DSS, PD_DSS)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DLL (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DMM (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF1 (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF2 (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF_OCP_FW (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CPGMAC (CD_GMAC, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPU (CD_GPU, PD_GPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : OFF
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C5 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP1 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER5 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER6 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER7 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER8 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART6 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IPU1 (CD_IPU1, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IPU2 (CD_IPU2, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IVA (CD_IVA, PD_IVA)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SL2 (CD_IVA, PD_IVA)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IEEE1500_2_OCP (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC2 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SATA (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS2 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS4 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CTRL_MODULE_BANDGAP (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DLL_AGING (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_INSTR (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_MAIN_2 (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP_WP_NOC (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPMC (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_MAIN_1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMU_EDMA (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMU_PCIESS (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM2 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM3 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPCC (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPTC1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPTC2 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_CFG (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP2 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SAR_ROM (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SPINLOCK (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IO_DELAY_BLOCK (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX1 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX10 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX11 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX12 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX13 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX2 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX3 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX4 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX5 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX6 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX7 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX8 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX9 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER10 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER11 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER9 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : ELM (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : HDQ1W (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART5 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO5 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO6 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO7 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO8 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DCAN2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART7 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART8 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART9 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PRUSS1 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PRUSS2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP3 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP4 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP5 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP6 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP7 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP8 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS1 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS3 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : QSPI (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER3 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER13 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER14 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER15 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER16 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : AES1 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : AES2 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DES3DES (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : RNG (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SHA2MD51 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SHA2MD52 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU (CD_MPU, PD_MPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU_MPU_DBG (CD_MPU, PD_MPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PCIESS1 (CD_PCIE, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PCIESS2 (CD_PCIE, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : RTCSS (CD_RTC, PD_RTC)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP1 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP2 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP3 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VPE (CD_VPE, PD_VPE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DEBUG_LOGIC (CD_EMU, PD_EMU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU_EMU_DBG (CD_EMU, PD_EMU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : COUNTER_32K (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CTRL_MODULE_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DCAN1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IO_SRCOMP_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : KBD (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SAR_RAM (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER12 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART10 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : WD_TIMER2 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
    Fullscreen 1300.NOT_WORKING_GEL_LOG.txt Download 
    CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output: ERROR: HW-Leveling time-out
CortexA15_0: GEL Output:        Two EMIFs in non interleaved mode (2GB total)
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 0: 0x00000000
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 1: 0x00000000
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 2: 0x00000000
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 3: 0x00000000
CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 4: 0x00000000
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 0: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 1: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 2: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 3: 0x0000007F
CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO  Macro 4: 0x0000007F
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 0: 0x00000077
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 1: 0x00000077
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 2: 0x00000077
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 3: 0x00000077
CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 4: 0x00000077
CortexA15_0: GEL Output: 
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 0: 0x00000057
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 1: 0x00000057
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 2: 0x00000057
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 3: 0x00000057
CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO  Macro 4: 0x00000057
CortexA15_0: GEL Output: 

CortexA15_0: GEL Output: -------------------------------------------------------
CortexA15_0: GEL Output:  PRCM State of all modules on the device
CortexA15_0: GEL Output: -------------------------------------------------------
CortexA15_0: GEL Output: Module : DMA_SYSTEM (CD_DMA, PD_CORE)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSP1 (CD_DSP1, PD_DSP1)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSP2 (CD_DSP2, PD_DSP2)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : BB2D (CD_DSS, PD_DSS)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DSS (CD_DSS, PD_DSS)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DLL (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DMM (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF1 (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF2 (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : EMIF_OCP_FW (CD_EMIF, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CPGMAC (CD_GMAC, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPU (CD_GPU, PD_GPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : OFF
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C5 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP1 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER5 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER6 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER7 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER8 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART6 (CD_IPU, PD_IPU)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IPU1 (CD_IPU1, PD_IPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IPU2 (CD_IPU2, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IVA (CD_IVA, PD_IVA)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SL2 (CD_IVA, PD_IVA)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IEEE1500_2_OCP (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC2 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SATA (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS2 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS3 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : USB_OTG_SS4 (CD_L3INIT, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CTRL_MODULE_BANDGAP (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DLL_AGING (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_INSTR (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_MAIN_2 (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP_WP_NOC (CD_L3INSTR, PD_CORE)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPMC (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L3_MAIN_1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMU_EDMA (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMU_PCIESS (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM2 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCMC_RAM3 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPCC (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPTC1 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TPTC2 (CD_L3MAIN1, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_CFG (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : OCP2SCP2 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SAR_ROM (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SPINLOCK (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IO_DELAY_BLOCK (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX1 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX10 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX11 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX12 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX13 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX2 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX3 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX4 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX5 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX6 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX7 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX8 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MAILBOX9 (CD_L4CFG, PD_CORE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : I2C4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER10 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER11 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER9 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : ELM (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : HDQ1W (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCSPI4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART1 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART5 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO2 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO5 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO6 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO7 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO8 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC3 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MMC4 (CD_L4PER, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DCAN2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART7 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART8 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART9 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PRUSS1 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PRUSS2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : STANDBY
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE AUTO CLOCK GATED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP3 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP4 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP5 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP6 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP7 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MCASP8 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS1 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS2 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PWMSS3 (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : QSPI (CD_L4PER2, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_PER3 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER13 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER14 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER15 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER16 (CD_L4PER3, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : AES1 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : AES2 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DES3DES (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : RNG (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SHA2MD51 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SHA2MD52 (CD_L4SEC, PD_L4PER)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU (CD_MPU, PD_MPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU_MPU_DBG (CD_MPU, PD_MPU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PCIESS1 (CD_PCIE, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : PCIESS2 (CD_PCIE, PD_L3INIT)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : RTCSS (CD_RTC, PD_RTC)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP1 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP2 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VIP3 (CD_CAM, PD_CAM)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : VPE (CD_VPE, PD_VPE)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DEBUG_LOGIC (CD_EMU, PD_EMU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : MPU_EMU_DBG (CD_EMU, PD_EMU)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : COUNTER_32K (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : CTRL_MODULE_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : DCAN1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : GPIO1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : IO_SRCOMP_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : Determined by Clock State
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : KBD (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : L4_WKUP (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : SAR_RAM (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER1 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : TIMER12 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : UART10 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : DISABLED
CortexA15_0: GEL Output: 	Clock State : OFF
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE DISABLED 
CortexA15_0: GEL Output: ==========================================
CortexA15_0: GEL Output: Module : WD_TIMER2 (CD_WKUPAON, PD_WKUPAON)
CortexA15_0: GEL Output: 	Module State : ON
CortexA15_0: GEL Output: 	Clock State : ON
CortexA15_0: GEL Output: 	Power State : ALWAYS ON
CortexA15_0: GEL Output: 	Final State : MODULE ALWAYS ENABLED 
CortexA15_0: GEL Output: ==========================================

  • 0 in reply to Jigar Patel
    TI__Mastermind 38600 points

    Hi,

    When you say "Working GEL" and "Not Working GEL", can you confirm that there is no difference in the GEL, and that the only difference is the hardware revision?

    You mentioned that you modified the following parameters. Is this all you have modified for your custom board? 

    "IS_EMIF2_AVAILABLE to 0"

    "MEMMAP_2GB_INTL_EMIFX2 to 0"

    "MEMMAP_2GB_NON_INTL_EMIFX2 to 1"

    It also appears that you are using default PHY values. As a debug step, can you please ensure that PHY_26 - PHY_35 are all set to 0? Can you also please make sure that all other values match with the XLS tool?

    "Revision R0 DDR RAM HW levelling Passed with default DDR PHY values"
    "Revision R1 DDR RAM HW levelling Failed and shows "ERROR: HW-Leveling time-out""

    Thanks,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 10 points

    When you say "Working GEL" and "Not Working GEL", can you confirm that there is no difference in the GEL, and that the only difference is the hardware revision?

    We are using same GEL file for both revision.Working GEL and Not Working GEL means board log for working and not working.

    There is no difference in GEL file.

    You mentioned that you modified the following parameters. Is this all you have modified for your custom board? 

    we are using default values for DDR RAM as required in EVM. No modification in DDR RAM timing.

    can you please ensure that PHY_26 - PHY_35 are all set to 0?

    As per line 266 in GEL file it remains 0 from EXT_PHY_CTRL_26 to EXT_PHY_CTRL_35

    Can you also please make sure that all other values match with the XLS tool?

    We are not modifying values from XLS in this tool as default values from EVM are working for Revision 0.

    While for uboot we have tries modifying values as per the output from XLS file but still the result remains same.

    Here is my AM572x_ddr_config.gel file

    1464.AM572x_ddr_config.gel

  • 0 in reply to Jigar Patel
    TI__Mastermind 38600 points

    Hi,

    Since the issue seems to follow R1, have you confirmed the hardware deltas between R0 and R1?

    Have you measured all voltages (or at least the major rails such as vdd_core, vdd_mpu, etc.) with a scope to ensure rails are within datasheet limits (measure as close to SOC as possible, as there could be a voltage drop on the board)?

    You may also consider checking the external oscillator is at correct frequency.

    From past experience, I believe there should be some initial print to the console before DDR is configured in u-boot; thus, I am not sure your u-boot issue is necessarily related to DDR (you could confirm this by dumping the EMIF registers at time of failure to see if they have been programmed with expected values - this can be done via JTAG). As such, it seems there may be multiple issues, which would point to a global problem. 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 10 points

    What we have checked uptill now.

    Power on sequence of all rails from pmic using logic analyzer. (As Expected per PMIC OFF2ACT sequence)
    Voltages of all rails (As Expected from PMIC)

    Not using uboot as for now because we might get into another issue so using only GEL file to bring up until HW leveling successfully completed.

    Changes in both Revision.
    In REV0 VDDA_USB2 was floating so connected VDDA_USB2 to VDDA_USB1 in REV1.
    In REV0 we have used a HDMI switch to genrate dual HDMI output from HDMI1 (It was working as expected) now we have removed switch as no more required in REV1.

    Crystal at OSC0 showing 20 MHz while at OSC1 showing 22.5 MHz as we have connected.

    Here is my power on sequence.

    Thanks

  • 0 in reply to Kevin S
    Prodigy 10 points

    Can you provide more details on further testing?

    Thanks,

  • 0 in reply to Jigar Patel
    TI__Mastermind 38600 points

    Hi,

    The previous suggestion was to verify that the voltages are within datasheet limits. It does not look like this has been performed yet.

    Can you check?

  • 0 in reply to Kevin S
    Prodigy 10 points

    I've already checked all voltage rails. see i've mentioned here.

    What we have checked uptill now.

Power on sequence of all rails from pmic using logic analyzer. (As Expected per PMIC OFF2ACT sequence)
-->  Voltages of all rails (As Expected from PMIC)

    Any other suggestions?

  • +1 in reply to Jigar Patel
    Prodigy 10 points

    Hello,

    We have resolved this issue.

    It seem faulty SDRAM.Replacing SDRAM works fine.

    Thanks