This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Cortex-A8 (OMAP3530) cache debugging

Other Parts Discussed in Thread: OMAP3530

Hi,

I'm debugging some performance issues and am attempting to get some insight into what is loaded into the L1 cache on the OMAP3530 (on a Beagleboard). I'm trying to use the c15 system array debug data registers, but they always throw an undefined exception fault when I try to use them. e.g.:

mcr p15, 0, r0, c15, c0, 0

My best guess is that I am not in a "secure" mode. I cannot access the Secure Configuration Register either (0, c1, c1, 0). I have tried accessing these from even x-loader and still get an undefined instruction exception. One forum thread seems to suggest that Secure mode is not possible on the Beagleboards: http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/58680/209901.aspx

Can anybody confirm if this is why I cannot access the debug registers? Is there any other way I can examine the contents of the L1 cache?

Thanks in advance,

Bernard.