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DRA76P: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 62c01908

Shantanu Joshi
Expert 1320 points
Part Number: DRA76P


Hello All,

I am working on custom DRA76P board, and my usecase is as follows,

UseCase: SVS_Main

CANLink

datatrans (A15)

while creating a CANLink I am facing the ### XDC ASSERT - ERROR CALLBACK START ### occurring from System_linkCreate().


I am debugging the usecase using GDB, attaching the log for the same. I am not getting where exactly this Hard Fault is occurring.

Your Inputs will be very helpful to resolve the issue.

Fullscreen CAN_Debug2_15042021.txt Download 
root@dra7xx-evm:/opt/vision_sdk# gdb ./apps.out 
GNU gdb (Linaro GDB) 7.8-2014.09
Copyright (C) 2014 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "arm-linux-gnueabi".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://bugs.linaro.org>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from ./apps.out...done.
(gdb) [   47.280289] random: nonblocking pool is initialized
b SVS_Main_Create
Breakpoint 1 at 0x1c154
(gdb) b System_linkCreate
Breakpoint 2 at 0x23642
(gdb) b System_linkCreate
Note: breakpoint 2 also set at pc 0x23642.
Breakpoint 3 at 0x23642
(gdb) b SVS_Main_StartApp
Breakpoint 4 at 0x1be38
(gdb) b ChainsCommon_statCollectorReset
Breakpoint 5 at 0x2126e
(gdb) b ChainsCommon_memPrintHeapStatus
Breakpoint 6 at 0x211d0
(gdb) b SVS_Main_Start
Breakpoint 7 at 0x1c226
(gdb) r
Starting program: /opt/vision_sdk/apps.out 
warning: Could not load shared library symbols for linux-vdso.so.1.
Do you need "set solib-search-path" or "set sysroot"?
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/libthread_db.so.1".
warning: File "/lib/libstdc++.so.6.0.21-gdb.py" auto-loading has been declined by your `auto-load safe-path' set to "$debugdir:$datadir/auto-load".
To enable execution of this file add
	add-auto-load-safe-path /lib/libstdc++.so.6.0.21-gdb.py
line to your configuration file "/home/root/.gdbinit".
To completely disable this security protection add
	set auto-load safe-path /
line to your configuration file "/home/root/.gdbinit".
For more information about this security protection see the
"Auto-loading safe path" section in the GDB manual.  E.g., run from the shell:
	info "(gdb)Auto-loading safe path"
 [HOST]  OSA: MEM: 0: Mapped 0x9fc00000 to 0xb6a1d000 of size 0x00100000 
 [HOST]  OSA: MEM: 1: Mapped 0x84203000 to 0xa611d000 of size 0x10900000 
 [HOST]  OSA: MEM: 2: Mapped 0x9fd00000 to 0xa605d000 of size 0x00040000 
 [HOST]  OSA: MEM: 3: Mapped 0x9fdc0000 to 0xa609d000 of size 0x00080000 
 [HOST]  OSA: MEM: 4: Mapped 0x00000000 to 0x00000000 of size 0x00000000 
 [HOST]  OSA: IPU1-0 Remote Log Shared Memory @ 0x9fd00000
 [HOST]  OSA: HOST Remote Log Shared Memory @ 0x9fd4f140
 [HOST]  OSA: DSP1 Remote Log Shared Memory @ 0x9fd769e0
[New Thread 0xa605c450 (LWP 983)]
[New Thread 0xa585c450 (LWP 985)]
[New Thread 0xa505c450 (LWP 987)]
 [HOST] [IPU1-0]     11.349630 s:  CHAINS: Application Started !!!
 [HOST] [IPU1-0]     11.374519 s:  
 [HOST] [DSP1  ]     10.963490 s: 
 [HOST] [DSP1  ]  AlgorithmLink_SurroundView3d_initPlugin start Time: 10963
 [HOST] [DSP1  ]     11.349630 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after boot !!!
 [HOST] [DSP1  ]     11.349661 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after update by APP !!!
[New Thread 0xa485c450 (LWP 989)]
[New Thread 0xa405c450 (LWP 991)]
[New Thread 0xa385c450 (LWP 992)]
[New Thread 0xa305c450 (LWP 993)]
[New Thread 0xa285c450 (LWP 994)]
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[New Thread 0x9a01c450 (LWP 1019)]
[New Thread 0x9981c450 (LWP 1020)][  160.919130] omap_l3_noc 44000000.ocp: L3 application error: target 3 mod:2 (unclearable)

[New Thread 0x9901c450 (LWP 1021)]
[New Thread 0x9881c450 (LWP 1022)]
[New Thread 0x9801c450 (LWP 1023)]
[New Thread 0x9781c450 (LWP 1024)]
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[New Thread 0x9681c450 (LWP 1026)]
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160.930618] omap_l3_noc 44000000.ocp: L3 debug error: target 3 mod:2 (unclearable)
[ HOST] [HOST  ]    165.064722 s: 
 [HOST] [HOST  ]  
 [HOST][HOST  ]  ====================
 [HOST] [HOST  ]  Vision SDK Usecases
 [HOST] [HOST  ]  ====================
 [HOST] [HOST  ]  1: 3DSVS
 [HOST] [HOST  ]  2: Offline
 [HOST] [HOST  ]  3: 3DSVS_Main
 [HOST] [HOST  ]  s: Set Vehical Speed
 [HOST] [HOST  ]  4: SoilDetection_Debug
 [HOST] [HOST  ]  5: 3DSVS_issCapture_Display
 [HOST] [HOST  ]  p: CPU Status
 [HOST] [HOST  ]  t: System Settings 
 [HOST] [HOST  ]  0: Exit 
 [HOST] [HOST  ]  z: Exit - AND SHUTDOWN Remote CPUs
 [HOST] [HOST  ]  
 [HOST] [HOST  ]  Enter Choice: 
 [HOST] [HOST  ]  
3

Breakpoint 1, 0x0001c154 in SVS_Main_Create ()
(gdb) n
Single stepping until exit from function SVS_Main_Create,
which has no line number information.
 [HOST] [HOST  ]    166.872537 s:  Inside SVS_Main_Display 
 [HOST] [HOST  ]    166.872537 s:  Before SVS_Main_Create 
 [HOST] [HOST  ]    170.187519 s: Inside SVS_Main_SetAppPrms
 [HOST] [HOST  ]    170.188159 s: Global ptr_virt = a611d200
 [HOST] [HOST  ]    170.188190 s: val = 84203200
 [HOST] [HOST  ]    170.188190 s: Address of cfgPrmsInMemory = 84203200

Breakpoint 2, 0x00023642 in System_linkCreate ()
(gdb) n
Single stepping until exit from function System_linkCreate,
which has no line number information.
[  177.460677] omap_l3_noc 44000000.ocp: L3 application error: target 22 mod:1 (unclearable)
 [HOST] [IPU1-0]    181.526932 s: 
 [HOST] [IPU1-0]    181.527023 s:  ### XDC ASSERT - ERROR CALLBACK START ### 
 [HOST] [IPU1-0]    181.527084 s: 
 [HOST] [IPU1-0]    181.527237 s: E_hardFault: FORCED
 [HOST] [IPU1-0]    181.527298 s: 
 [HOST] [IPU1-0]    181.527328 s:  ### XDC ASSERT - ERROR CALLBACK END ### 
 [HOST] [IPU1-0]    181.527389 s: 
 [HOST] [IPU1-0]    181.527603 s: 
 [HOST] [IPU1-0]    181.527633 s:  ### XDC ASSERT - ERROR CALLBACK START ### 
 [HOST] [IPU1-0]    181.527725 s: 
 [HOST] [IPU1-0]    181.527816 s: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 62c01908
 [HOST] [IPU1-0]    181.527938 s: 
 [HOST] [IPU1-0]    181.527969 s:  ### XDC ASSERT - ERROR CALLBACK END ### 
 [HOST] [IPU1-0]    181.528030 s:


Regards,

Shantanu Joshi

  • 0
    TI__Guru 50045 points

    Hi,

    From the log, the XDC assertion occurs on IPU1_0 during the link creation.

    Can you check your case and find out which link is created on IPU1_0?

    The Links will be created one by one and you can add some trace in each link to find out which Link created on IPU1_0 generated the XDC assertion.

    From the error log, it looks like that link was accessing invalid address at 0x62c01908.

    [HOST] [IPU1-0] 181.527633 s: ### XDC ASSERT - ERROR CALLBACK START ###
    [HOST] [IPU1-0] 181.527725 s:
    [HOST] [IPU1-0] 181.527816 s: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 62c01908
    [HOST] [IPU1-0] 181.527938 s:
    [HOST] [IPU1-0] 181.527969 s: ### XDC ASSERT - ERROR CALLBACK END ###

    Regards,
    Stanley

  • 0 in reply to Stanley Liu
    Expert 1320 points

    Hi Stanley

    XDC assert is coming from the following routine,

    uint32_t MCAN_isFDOpEnable(uint32_t baseAddr)
    {
    uint32_t fdoe;
    uint32_t state;

    fdoe = HW_RD_FIELD32(baseAddr + MCAN_MCANSS_STAT,
    MCAN_MCANSS_STAT_ENABLE_FDOE);
    if (1U == fdoe)
    {
    state = (uint32_t) TRUE;
    }
    else
    {
    state = (uint32_t) FALSE;
    }
    return state;
    }

    baseAddr passed is (0x42C00000U + 0x20000000U)

    Regards

    Shantanu

  • 0 in reply to Shantanu Joshi
    Expert 1320 points

    Hi,

    Please note that this usecase is running on HLOS.

    We have faced the similar issue earlier for RTOS usecase and that gets resolved when we uncommented following block from file at path,

    vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg

    block uncommented is,

    var entry = AMMU.largePages[3];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x60000000;
    entry.translatedAddress = 0x40000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    what needs to be done for HLOS usecase in order to make it work as right now CAN FD is not getting enabled and address 0x62c01908 for MCAN_MCANSS_STAT register is giving Hard Fault.

    Regards

    Shantanu

  • +1 in reply to Shantanu Joshi
    TI__Guru 50045 points

    Hi,

    For IPU to access MCAN register @ 0x42C0_0000 region, the base address has to be remapped to 0x6xxx_xxxx region via AMMU.

    This is because 0x4000_0000 region is IPU_BITBAND_REGION2 in IPU Memory Map. This is regardless HLOS or RTOS use case.

    Secondly, the MCAN module clock has to be enabled before MCAN registers can be accessed.

    How did you enable MCAN module for RTOS use case? You have to do the same for HLOS use case.

    Regards,
    Stanley

  • 0 in reply to Stanley Liu
    Expert 1320 points

    Hi Stanley,

    We are enabling the clock in padConfigPrcmEnable() routine like below,


    Void padConfigPrcmEnable(Void)
    {

    /*Pad configurations - MCAN */
    /* Configure mcan_tx, mcan_rx pads on dcan1_tx and dcan1_rx pads */

    Vps_printf(" \n SSD_ITS: padConfigPrcmEnable start");

    HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW,
    CTRL_CORE_CONTROL_SPARE_RW_SEL_ALT_MCAN,
    CTRL_CORE_CONTROL_SPARE_RW_SEL_ALT_MCAN_MCAN_GPIO6_PADS);

    HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_GPIO6_14, 0x00040002);
    HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_GPIO6_15, 0x00040002);

    // HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_GPMC_ADVN_ALE,0x0000000E);
    /*CTRL_CORE_PAD_GPMC_ADVN_ALE */
    //GPIODirModeSet( SOC_GPIO2_BASE, 23U, GPIO_DIR_OUTPUT);
    // GPIOPinWrite( SOC_GPIO2_BASE, 23U, GPIO_PIN_LOW);

    /* Enable MCAN clock. */
    HW_WR_FIELD32(SOC_WKUPAON_CM_BASE + CM_WKUPAON_ADC_CLKCTRL,
    CM_WKUPAON_ADC_CLKCTRL_MODULEMODE,
    CM_WKUPAON_ADC_CLKCTRL_MODULEMODE_ENABLE);
    while (CM_WKUPAON_ADC_CLKCTRL_IDLEST_FUNC !=
    HW_RD_FIELD32(SOC_WKUPAON_CM_BASE + CM_WKUPAON_ADC_CLKCTRL,
    CM_WKUPAON_ADC_CLKCTRL_IDLEST))
    {
    /* wait for module to be enabled */
    }
    Vps_printf(" \n SSD_ITS: padConfigPrcmEnable end");
    }

    Please note that this pin config is same as that of we were using for RTOS usecase. 

    Yes we are enabling the MCAN clock before accessing the MCAN registers. 

    Regards,

    Shantanu

  • 0 in reply to Shantanu Joshi
    Expert 1320 points

    Hi Stanley,

    The issue is resolved now.

    We were setting 

    #define MCAN_SEL     0x4000 instead of 0x2000 for selecting DCAN2 as MCAN in mux_dra7xx.h

    Reverting the changes and keeping the default value as 0x2000 resolved my issue.

    Thank you for the assistance. I will close the thread now.

    Regards,

    Shantanu