TDA2P-ACD: SJA1105q device tree config

Hello,

We have a custom board that uses NXP SJA1105q switche. The cpu port of the switche are connected to "cpsw_port1" on TDA2P-ACD, however I configure this in the "cpu" port in the device tree, the dsa framework (dsa2.c) keeps failing in (of_find_net_device_by_node(ethernet);).

I examined the other device trees using the same switch (ls1021a-tsn.dts)&(imx6qp-prtwd3.dts) and it is clear that they are passing a phandle to a valid Ethernet device node to the ethernet property under the cpu port.

I tried to pass cpsw_port1, mac_sw to "ethernet" property to the cpu port in the switch node but this always fails.

How can I satisfy the ethernet property requirement in "./Documentation/devicetree/bindings/net/dsa/dsa.yaml" with this dual_mac switch ?

Below is network configuration section in my dts:

&mcspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi3_pins>;
	status = "okay";
	ti,pindir-d0-out-d1-in = <1>;

	switch1: switch@0 {
		compatible = "nxp,sja1105q";
		reg = <0>;
		spi-max-frequency = <4000000>;
		spi-rx-delay-us = <1>;
		spi-tx-delay-us = <1>;
		fsl,spi-cs-sck-delay = <1000>;
		fsl,spi-sck-cs-delay = <1000>;

	/*	The interface operate
	        in SPI Transfer mode 1 
		(CPOL = 0, CPHA = 1)  */
		spi-cpha;
		reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
		clocks = <&clock_sja1105>; 

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				/* ETH5 written on chassis */
				reg = <0>;
				label = "swp1";
				phy-handle = <&rgmii_phy1>;
				phy-mode = "rgmii";
				sja1105,role-mac;
			};
			port@1 {
				/* ETH2 written on chassis */
				reg = <1>;
				label = "swp2";
				phy-handle = <&rgmii_phy2>;
				phy-mode = "rgmii";
				sja1105,role-mac;
			};
			port@2 {
				/* ETH3 written on chassis */
				reg = <2>;
				label = "swp3";
				phy-handle = <&rgmii_phy3>;
				phy-mode = "rgmii";
				sja1105,role-mac;
			};
			port@3 {
				/* ETH4 written on chassis */
				reg = <3>;
				phy-handle = <&rgmii_phy4>;
				label = "swp4";
				phy-mode = "rgmii";
				sja1105,role-mac;
			};
			switch1port4: port@4 {
				/* Internal port connected to eth2 */
				reg = <4>;
				phy-mode = "rgmii";
				label = "cpu";
				ethernet = <&cpsw_port1>;
				sja1105,role-phy;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};
};




/* Configuration of DRA7 build in DUAL-MAX-SWITCH */

&mac_sw {
	status = "okay";   
};

&cpsw_port1 {
    	phy-handle = <&switch1port4>;
    	phy-mode = "rgmii";
	status = "okay";
	ti,dual-emac-pvid = <1>;

	fixed-link {
 		speed = <1000>;
		full-duplex;
	};
	
};

&cpsw_port2 {
	status = "disabled"; 
	
};

Note that the switch is probed and the chip id is read properly.