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XDS510PP issues connecting to C6402

Ignacio Linares
Expert 1655 points


I have a customer asking the following questions.  He is using CCS v.2.x which is the same that he has used on past designs with the same DSP:

I am currently seeing the following issues while using the XDS510PP emulator: 

-          I can access the Internal Data Ram space at 0x80001000

-          I cannot access the Internal Program Ram space which should be configured via the BOOTMODE pins to be at address 0.  I always read 0xFFFFFFFF and cannot modify the value.

-          I cannot access the EMIF registers at 0x01800000.  When I attempt to read these registers, I always read the value 0x41101107 and cannot modify the value.

-          When I attempt to access any peripheral device, either the Flash or the FPGA on the card, I do not see the any of the chip enables activated or the address put out on the bus. 

I’m sure this is probably a boot up configuration issue, but I’m running out of ideas to look at.  Any help you can provide would be greatly appreciated.

 

 

 

 

 

  • 0
    Expert 1655 points

    Correction on title.  Should be C6204 DSP.

  • 0
    TI__Mastermind 18130 points

    Iggy,

    I have seen this type of behavior before but I do not recall there being a specific reason for it. In general I suggest double-checking all of the boot pins as well as the Reserved lines to make sure nothing is wired incorrectly. I have seen cases where a Reserved line was pulled high or low coming out of reset, and this caused the device to go into some sort of test state which behaved nothing like expected. Most devices have very strict guidelines regarding these types of pins in the datasheet. As an example, the pins listed in the Signal Descriptions on p26 of the datasheet all have specific requirements.

    Additionally, power sequencing can play a big part in unexpected behavior like this. The C6204 does not have any specific power sequencing requirements other than not bringing up one much earlier than the other (p38 datasheet), but in my experience I seem to recall issues where the I/O was brought up much earlier than the core (and/or vice versa).

    One other thing is if a GEL file is in use a lot of times the Memory Map can be a cause of problems. CCS has what I call a virtual memory map which it uses as a sort of error-checking to prevent the programmer from accessing invalid memory. The GEL_MapAdd() functions are used to define valid memory ranges, and by default everything else is invalid. For peripheral access a lot of times the GEL file is responsible for proper configuration, so this could be a cause of issue if using the wrong GEL config, etc.

  • 0 in reply to TimHarron
    Expert 1655 points

    correct boot pin configuration resolved the issue.