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AM4378: Unable to get the status of clkreq GPIO.

Monish27
Intellectual 636 points
Part Number: AM4378

Hi,

In our custom board, we are able to check the status of all the GPIO in u-boot except the one GPIO i.e, clkreq (H20) using gpio input 24 command.

The pin status was always 0. And when we checked the datasheet regarding clkeq , this pin is clkreq (MODE0) after reset. 

I u-boot dts, I have configured this pin as input and MODE7 to work as GPIO. Please find the below dts configuration in u-boot.

 gpio0_pins: gpio0_pins {
  pinctrl-single,pins = <
   0x108 (PIN_INPUT | MUX_MODE7) /* (D16) mii1_col.gpio0[0] */
   0x158 (PIN_OUTPUT | MUX_MODE7) /* (T21) spi0_d1.gpio0[4] */
   0x15c (PIN_OUTPUT | MUX_MODE7) /* (T20) spi0_cs0.gpio0[5] */
   0x160 (PIN_OUTPUT | MUX_MODE7) /* (R25) spi0_cs1.gpio0[6] */
   0x2c0 (PIN_INPUT | MUX_MODE7) /* (g21) USB0DRVBUS.gpio0[18] */
   0x264 (PIN_OUTPUT | MUX_MODE7) /* (P22) spi2_d0.gpio0[20] */
   0x268 (PIN_OUTPUT | MUX_MODE7) /* (P20) spi2_d1.gpio0[21] */
   0x260 (PIN_OUTPUT | MUX_MODE7) /* (N20) spi2_sclk.gpio0[22] */
   0x26c (PIN_OUTPUT | MUX_MODE7) /* (T23) spi2_cs0.gpio0[23] */
   0x278 (PIN_INPUT | MUX_MODE7) /* (H20) clkreq.gpio0[24] */
   0x2c4 (PIN_OUTPUT | MUX_MODE7) /* (F25) USB1_DRVVBUS.gpio0[25] */
   0x144 (PIN_OUTPUT | MUX_MODE7) /* (A16) rmii1_ref_clk.gpio0[29] */
  
  >;
 };

Is there any other changes need to do in u-boot dts or mux.c to get the status of the pin correctly.

  • 0
    TI__Guru 68430 points

    Hi Monish,
    Can you upload to attachment the log file when running "gpio status -a" @u-boot prompt
    Best,
    -Hong

  • 0 in reply to Hong Guan64
    Intellectual 636 points

    Hi Hong,

    Please find the attached log.

    => gpio status -a
    Bank gpio@44e07000_:
    gpio@44e07000_0: input: 0 [ ]
    gpio@44e07000_1: input: 0 [ ]
    gpio@44e07000_2: input: 0 [ ]
    gpio@44e07000_3: input: 0 [ ]
    gpio@44e07000_4: input: 1 [ ]
    gpio@44e07000_5: input: 1 [ ]
    gpio@44e07000_6: input: 1 [ ]
    gpio@44e07000_7: input: 1 [ ]
    gpio@44e07000_8: input: 0 [ ]
    gpio@44e07000_9: input: 0 [ ]
    gpio@44e07000_10: input: 1 [ ]
    gpio@44e07000_11: input: 0 [ ]
    gpio@44e07000_12: input: 1 [ ]
    gpio@44e07000_13: input: 1 [ ]
    gpio@44e07000_14: input: 1 [ ]
    gpio@44e07000_15: input: 1 [ ]
    gpio@44e07000_16: input: 0 [ ]
    gpio@44e07000_17: input: 0 [ ]
    gpio@44e07000_18: output: 1 [x] cmd_gpio
    gpio@44e07000_19: input: 0 [ ]
    gpio@44e07000_20: input: 0 [ ]
    gpio@44e07000_21: input: 0 [ ]
    gpio@44e07000_22: input: 0 [ ]
    gpio@44e07000_23: input: 0 [ ]
    gpio@44e07000_24: input: 0 [ ]
    gpio@44e07000_25: input: 0 [ ]
    gpio@44e07000_26: input: 0 [ ]
    gpio@44e07000_27: input: 0 [ ]
    gpio@44e07000_28: input: 0 [ ]
    gpio@44e07000_29: input: 0 [ ]
    gpio@44e07000_30: input: 1 [ ]
    gpio@44e07000_31: input: 0 [ ]

    Bank gpio@4804c000_:
    gpio@4804c000_0: input: 0 [ ]
    gpio@4804c000_1: input: 1 [ ]
    gpio@4804c000_2: input: 0 [ ]
    gpio@4804c000_3: input: 1 [ ]
    gpio@4804c000_4: input: 0 [ ]
    gpio@4804c000_5: input: 0 [ ]
    gpio@4804c000_6: input: 1 [ ]
    gpio@4804c000_7: input: 0 [ ]
    gpio@4804c000_8: input: 1 [ ]
    gpio@4804c000_9: input: 1 [ ]
    gpio@4804c000_10: input: 0 [ ]
    gpio@4804c000_11: input: 0 [ ]
    gpio@4804c000_12: input: 0 [ ]
    gpio@4804c000_13: input: 0 [ ]
    gpio@4804c000_14: input: 0 [ ]
    gpio@4804c000_15: input: 0 [ ]
    gpio@4804c000_16: input: 0 [ ]
    gpio@4804c000_17: input: 0 [ ]
    gpio@4804c000_18: input: 0 [ ]
    gpio@4804c000_19: input: 0 [ ]
    gpio@4804c000_20: input: 0 [ ]
    gpio@4804c000_21: input: 0 [ ]
    gpio@4804c000_22: input: 0 [ ]
    gpio@4804c000_23: input: 0 [ ]
    gpio@4804c000_24: input: 0 [ ]
    gpio@4804c000_25: input: 0 [ ]
    gpio@4804c000_26: input: 0 [ ]
    gpio@4804c000_27: input: 0 [ ]
    gpio@4804c000_28: input: 1 [ ]
    gpio@4804c000_29: input: 0 [ ]
    gpio@4804c000_30: input: 0 [ ]
    gpio@4804c000_31: input: 0 [ ]

    Bank gpio@481ac000_:
    gpio@481ac000_0: input: 1 [ ]
    gpio@481ac000_1: input: 1 [ ]
    gpio@481ac000_2: input: 0 [ ]
    gpio@481ac000_3: input: 0 [ ]
    gpio@481ac000_4: input: 1 [ ]
    gpio@481ac000_5: input: 1 [ ]
    gpio@481ac000_6: input: 1 [ ]
    gpio@481ac000_7: input: 0 [ ]
    gpio@481ac000_8: input: 1 [ ]
    gpio@481ac000_9: input: 0 [ ]
    gpio@481ac000_10: input: 1 [ ]
    gpio@481ac000_11: input: 0 [ ]
    gpio@481ac000_12: input: 0 [ ]
    gpio@481ac000_13: input: 0 [ ]
    gpio@481ac000_14: input: 0 [ ]
    gpio@481ac000_15: input: 0 [ ]
    gpio@481ac000_16: input: 0 [ ]
    gpio@481ac000_17: input: 0 [ ]
    gpio@481ac000_18: input: 0 [ ]
    gpio@481ac000_19: input: 0 [ ]
    gpio@481ac000_20: input: 0 [ ]
    gpio@481ac000_21: input: 0 [ ]
    gpio@481ac000_22: input: 0 [ ]
    gpio@481ac000_23: input: 0 [ ]
    gpio@481ac000_24: input: 0 [ ]
    gpio@481ac000_25: input: 0 [ ]
    gpio@481ac000_26: input: 0 [ ]
    gpio@481ac000_27: input: 0 [ ]
    gpio@481ac000_28: input: 1 [ ]
    gpio@481ac000_29: input: 1 [ ]
    gpio@481ac000_30: input: 1 [ ]
    gpio@481ac000_31: input: 1 [ ]

    Bank gpio@481ae000_:
    gpio@481ae000_0: input: 1 [ ]
    gpio@481ae000_1: input: 0 [ ]
    gpio@481ae000_2: input: 0 [ ]
    gpio@481ae000_3: input: 0 [ ]
    gpio@481ae000_4: input: 0 [ ]
    gpio@481ae000_5: input: 0 [ ]
    gpio@481ae000_6: input: 0 [ ]
    gpio@481ae000_7: input: 0 [ ]
    gpio@481ae000_8: input: 0 [ ]
    gpio@481ae000_9: input: 0 [ ]
    gpio@481ae000_10: input: 0 [ ]
    gpio@481ae000_11: input: 0 [ ]
    gpio@481ae000_12: input: 0 [ ]
    gpio@481ae000_13: input: 0 [ ]
    gpio@481ae000_14: input: 0 [ ]
    gpio@481ae000_15: input: 0 [ ]
    gpio@481ae000_16: input: 0 [ ]
    gpio@481ae000_17: input: 0 [ ]
    gpio@481ae000_18: input: 0 [ ]
    gpio@481ae000_19: input: 0 [ ]
    gpio@481ae000_20: input: 0 [ ]
    gpio@481ae000_21: input: 0 [ ]
    gpio@481ae000_22: input: 0 [ ]
    gpio@481ae000_23: input: 1 [ ]
    gpio@481ae000_24: input: 0 [ ]
    gpio@481ae000_25: input: 1 [ ]
    gpio@481ae000_26: input: 0 [ ]
    gpio@481ae000_27: input: 0 [ ]
    gpio@481ae000_28: input: 0 [ ]
    gpio@481ae000_29: input: 0 [ ]
    gpio@481ae000_30: input: 0 [ ]
    gpio@481ae000_31: input: 0 [ ]

    Bank gpio@48320000_:
    gpio@48320000_0: input: 0 [ ]
    gpio@48320000_1: input: 0 [ ]
    gpio@48320000_2: input: 0 [ ]
    gpio@48320000_3: input: 0 [ ]
    gpio@48320000_4: input: 0 [ ]
    gpio@48320000_5: input: 0 [ ]
    gpio@48320000_6: input: 0 [ ]
    gpio@48320000_7: input: 0 [ ]
    gpio@48320000_8: input: 0 [ ]
    gpio@48320000_9: input: 0 [ ]
    gpio@48320000_10: input: 0 [ ]
    gpio@48320000_11: input: 0 [ ]
    gpio@48320000_12: input: 0 [ ]
    gpio@48320000_13: input: 0 [ ]
    gpio@48320000_14: input: 0 [ ]
    gpio@48320000_15: input: 1 [ ]
    gpio@48320000_16: input: 0 [ ]
    gpio@48320000_17: input: 0 [ ]
    gpio@48320000_18: input: 0 [ ]
    gpio@48320000_19: input: 0 [ ]
    gpio@48320000_20: input: 0 [ ]
    gpio@48320000_21: input: 1 [ ]
    gpio@48320000_22: input: 0 [ ]
    gpio@48320000_23: input: 0 [ ]
    gpio@48320000_24: input: 0 [ ]
    gpio@48320000_25: input: 0 [ ]
    gpio@48320000_26: input: 1 [ ]
    gpio@48320000_27: input: 0 [ ]
    gpio@48320000_28: input: 0 [ ]
    gpio@48320000_29: input: 0 [ ]
    gpio@48320000_30: input: 0 [ ]
    gpio@48320000_31: input: 0 [ ]

    Bank gpio@48322000_:
    gpio@48322000_0: input: 1 [ ]
    gpio@48322000_1: input: 1 [ ]
    gpio@48322000_2: input: 1 [ ]
    gpio@48322000_3: input: 1 [ ]
    gpio@48322000_4: input: 0 [ ]
    gpio@48322000_5: input: 1 [ ]
    gpio@48322000_6: input: 1 [ ]
    gpio@48322000_7: input: 1 [ ]
    gpio@48322000_8: input: 1 [ ]
    gpio@48322000_9: input: 1 [ ]
    gpio@48322000_10: input: 0 [ ]
    gpio@48322000_11: input: 0 [ ]
    gpio@48322000_12: input: 0 [ ]
    gpio@48322000_13: input: 1 [ ]
    gpio@48322000_14: input: 0 [ ]
    gpio@48322000_15: input: 0 [ ]
    gpio@48322000_16: input: 0 [ ]
    gpio@48322000_17: input: 0 [ ]
    gpio@48322000_18: input: 0 [ ]
    gpio@48322000_19: input: 0 [ ]
    gpio@48322000_20: input: 0 [ ]
    gpio@48322000_21: input: 0 [ ]
    gpio@48322000_22: input: 0 [ ]
    gpio@48322000_23: input: 0 [ ]
    gpio@48322000_24: input: 0 [ ]
    gpio@48322000_25: input: 0 [ ]
    gpio@48322000_26: input: 0 [ ]
    gpio@48322000_27: input: 0 [ ]
    gpio@48322000_28: input: 0 [ ]
    gpio@48322000_29: input: 0 [ ]
    gpio@48322000_30: input: 0 [ ]
    gpio@48322000_31: input: 0 [ ]

  • 0 in reply to Monish27
    TI__Guru 68430 points

    Hi Monish,
    Can we run a quick test using the following cmds @u-boot prompt to
    1. Check CM PINMUX configuration register CTRL_CONF_CLKREQ (0x44E10A78) is configured for GPIO0_24 as input?
    2. Read directly GPIO_0 bank registers GPIO_OE (0x44E07134) & GPIO_DATAIN (0x44E07138)

    md.l 0x44E10A78 1
md.l 0x44E07134 1
md.l 0x44E07138 1

    Best,

    -Hong

  • 0 in reply to Hong Guan64
    Intellectual 636 points

    Hi Hong,

    Please find the below result.

    => md.l 0x44e10a78 1
    44e10a78: 00010007 ....
    => md.l 0x44e07134 1
    44e07134: ffffffff ....
    => md.l 0x44e07138 1
    44e07138: 4000f4f0 ...@
    =>
  • 0 in reply to Monish27
    TI__Guru 68430 points

    Hi Monish,
    There seems a PINMUX misconfiguration for the pin "H20" in CTRL_CONF_CLKREQ (0x44E10A78).
    Can we run "mw.l 0x44e10a78 0x00050007 1" @u-boot prompt, and then run GPIO0_24 input test on your board?
    Best,
    -Hong

  • 0 in reply to Hong Guan64
    Intellectual 636 points

    Hi Hong,

    When I run the above command, I am able to get the status of the pin correct.

    In dts, I configured 0x278 (PIN_INPUT | MUX_MODE7) /* (H20) clkreq.gpio0[24] */

    And in mux.c, I configured {OFFSET(clkreq), (MODE(7) | PULLUDDIS)}.

    Is my configuration are correct?

  • 0 in reply to Monish27
    TI__Guru 68430 points

    Hi Monish,
    So PINMUX on the ball "H20" can be configured manually @u-boot prompt as GPIO0_24 input, and GPIO0_24 works on your board.

    Monish27 said:
    And in mux.c, I configured {OFFSET(clkreq), (MODE(7) | PULLUDDIS)}.

    Can we add "RXACTIVE" bit into the above line as listed below, and re-test?
    {OFFSET(clkreq), (MODE(7) | PULLUDDIS | RXACTIVE)}.
    Best,
    -Hong

  • 0 in reply to Hong Guan64
    Intellectual 636 points

    Hi Hong,

    Still, the problem is the same. The status of the clkreq pin is not changing by doing the changes you suggested.

    Regards

    Monish P

  • 0 in reply to Monish27
    TI__Guru 68430 points

    Hi Monish,
    I modified pinmux using the attached patch on AM437x GP EVM, and pinmux for the ball "H20" as "gpio0_24 input" works as listed below:
    => md.l 0x44e10a78 1
    44e10a78: 00050007 ....
    Best,
    -Hong

    Fullscreen am4_gpio0_24.patch.txt Download 
    diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index a61987e4c6..8457b209b6 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -73,6 +73,11 @@ static struct module_pin_mux gpio5_7_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux gpio0_24_pin_mux[] = {
+	{OFFSET(clkreq), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* GPIO0_24 */
+	{-1},
+};
+
 #ifdef CONFIG_NAND
 static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
@@ -128,6 +133,7 @@ void enable_board_pin_mux(void)
 	if (board_is_evm()) {
 		configure_module_pin_mux(gpio5_7_pin_mux);
 		configure_module_pin_mux(rgmii1_pin_mux);
+		configure_module_pin_mux(gpio0_24_pin_mux);
 #if defined(CONFIG_NAND)
 		configure_module_pin_mux(nand_pin_mux);
 #endif