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AM3352: AM335x NAND boot question

Part Number: AM3352


Hi Expert,

According to AM335x NAND boot feature requirement in datasheet:

Flash boot Support for large page size (2048 bytes + 64 spare bytes) or very large page size 4096 bytes + 128 /218 spare bytes)

My question is if Flash page size is 2048 bytes + 128 spare bytes, can BOOTROM support this flash boot?

Thanks,

Thomas

  • I am the originator of this issue, some supplement:

    To write the bootloader into NAND Flash , the board is boot up with SD card first, this SD card has a file which includes the NAND Flash SPL/UBoot data.

    NAND Flash SPL/UBoot data.will be read out from file and written into NAND Flash after board is boot up with SD card.

    After SPL/UBoot data. has been written to NAND Flash, board will be switched to boot from NAND flash.

    This method works well with AM335x and Micron NAND Flash MT29F2G08ABAEAWP, Page size x8: 2112 bytes (2048 + 64 bytes).

    Now we are trying to replace MT29F2G08ABAEAWP with MT29F2G08ABAGAWP, Page size x8: 2176 bytes (2048 + 128 bytes).

    We are using the same method as before, NAND Flash SPL/UBoot data.on SD card can be written into MT29F2G08ABAEAWP successfully.

    We verified the data in NAND flash both in program and JTAG debugger, the data in flash is EXACTLY same as the data in file.

    However, after board is switched to boot from NAND flash, SPL/UBoot can't be executed correctly, no debug information from debug serial port.

    We verify the whole process on old board again, it works well, debug information can be received at debug serial port.

     

    Can you help to answer If AM335x can work together with MT29F2G08ABAGAWP? If yes, any SYSBOOT_CFG register value need be changed comparing

    with MT29F2G08ABAEAWP ?

    Thanks for support!

  • Are you using the same image to flash both NANDs?  I think what may be happening is that you are using an image that contains the ECC data for a 64byte spare area region.  You would have to create a new NAND image that contains ECC for a 128byte spare area region (the formatting is different for a 128byte spare area, see figure 26-20 and figure 26-21 of the AM335x TRM).

    Or you could let the NAND handle the ECC.  I checked the NAND datasheet and it looks like it internal ECC is an option that is supported.  If allowing the NAND to handle ECC, this would require a change in the BOOTMODE bit9 (see table 26-18)

    Regards,

    James

  • Thanks for suggestion, we will check it out and feedback later

  • Could you give us more details or explanations? Actually, I used the same image(SPL) to flash both NANDs, The NAND with 64 bytes spare area can work well. We write 58bytes consecutively, first two bytes are bad block marker, and last 56bytes are ECC codes, (every 512 bytes to generate 14 bytes ECC codes, page size is 2k,AM3352 handle the ECC), now I tested two alternative NANDs, Both those chips' pagesize is 2k, and the spare area size is 128bytes, also write the same 58bytes consecutively to 128 bytes OOB, but is seems that ROMBOOT cannot find SPL image, could you tell me what ECC formatting difference between the NAND with 64 byte and with 128bytes?

  • I have changed my SPL and Uboot  to support BCH16 and I found ROMBOOT could load SPL successfully, I think ROMBOOT will check a NAND's spare space when it is runnning, if the spare space exceeds 64 bytes, ROMBOOT will use BCH16 rather than BCH8, I was wondering  that is there other ways to force  ROMBOOT to use BCH8 to load NAND's SPL, something like hardware design, or config some registers when ROMBOOT loads SPL image in MMC/SD.

  • Hi James

    #1,According to TRM info “For device ID codes D3h, C3h, D5h, C5h, D7h, C7h, DEh, CEh when manufacturer code (first ID byte) is
    98h the Cell type information is checked in the 4th byte of ID data. If it is equal to 10b then the ECC
    correction applied is BCH 16b/sector.” The ECC method which BootROM will choose BCH8 or BCH16 is based on the device ID.

    #2,According to Figure 26-16." ECC Data Mapping for 4 KB Page and 16b BCH Encoding ", The spare bytes support for BCH16 is 218B spare for 4K page, for 2K page +128B spare, it doesn't mention it. To me, for 2K page + 128 spare bytes, if the device ID is equal to the ID mentioned in #1 , then it will still use BCH16, right?

  • I think you are mixing the operation of the NANDI2C boot.  For NAND boot, if the ONFI command read is successful, the ROM will base the BCH off of the ONFI parameters and the page size (including the spare area).  There is no way to change this behavior

    Regards,

    James

  • you have mentioned that "If the ONFI command read is successful, the BootRom will boot the SPL based on the ONFI parameters and the page size including the spare area", Could you give us more information about that. I would like to know how BootRom checks these parameters and the page size (including spare space size), what rules or strategies the BootRom uses, because in the future if we choose new NANDs again, we still do not know if the BootRom choose ECH8 or ECH16 to load SPL?     

  • Jing, it determine BCH with the following formula:

    if (SpareBytesPerPage-2) >= (SectorsPerPage * 26)

    BCH16 is chosen

    else

    BCH8 is chosen

    where

    SpareBytesPerPage: is read from the ONFI parameters

    SectorsPerPage: Number of 512 byte sectors per page (eg, 2KB page would have 4 sectors)

    Regards,

    James