J721EXSOMXEVM: device tree for PCM6260

Hi Satish,

Sorry for the delay in response.

Can you tell me

1. Which SDK version is this ?

2. Can you provide the diff for the DT and any other changes that you might have done ?

Regards

Vineet

Hi Vineet,

We are using SDK 7.1. Here is the diff of my device tree -

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index d1a2eb4153b0..3fddd0399462 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -13,8 +13,8 @@
 
 / {
        chosen {
-               stdout-path = "serial2:115200n8";
-               bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+               stdout-path = "serial9:115200n8";
+               bootargs = "console=ttyS9,115200n8 earlycon=ns16550a,mmio32,0x02870000";
        };
 
        gpio_keys: gpio-keys {
@@ -189,151 +189,313 @@
                >;
        };
 
-       main_i2c1_pins_default: main-i2c1-pins-default {
+       main_i2c6_pins_default: main-i2c6-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
+                       J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
+               >;
+       };  
+
+       vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+               >;
+       };
+
+       /* Pointing to IVP HW */
+       uart0_backplane_coex61_pins_default: uart0_backplane_coex61_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x4, PIN_INPUT, 14) /* (AC23) PRG1_PRU0_GPO0.UART0_RXD */
+                       J721E_IOPAD(0x8, PIN_OUTPUT, 14) /* (AG22) PRG1_PRU0_GPO1.UART0_TXD */
+               >;
+       }; 
+
+       /* Pointing to IVP HW */
+       uart1_backplane_coex60_pins_default: uart1_backplane_coex60_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0xc, PIN_INPUT, 14) /* (AF22) PRG1_PRU0_GPO2.UART1_RXD */
+                       J721E_IOPAD(0x10, PIN_OUTPUT, 14) /* (AJ23) PRG1_PRU0_GPO3.UART1_TXD */
+               >;
+       }; 
+
+       /* Pointing to IVP HW */
+       uart2_bckplane_coex70_pins_default: uart2_bckplane_coex70_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x14, PIN_INPUT, 14) /* (AH23) PRG1_PRU0_GPO4.UART2_RXD */
+                       J721E_IOPAD(0x1c, PIN_OUTPUT, 14) /* (AD22) PRG1_PRU0_GPO6.UART2_TXD */
+               >;
+       };
+
+
+
+       /* Pointing to IVP HW */
+       uart3_backplane_rif0_pins_default: uart3_backplane_rif0_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0xb8, PIN_INPUT, 8) /* (AE27) PRG0_PRU0_GPO2.UART3_RXD */
+                       J721E_IOPAD(0xbc, PIN_OUTPUT, 8) /* (AD26) PRG0_PRU0_GPO3.UART3_TXD */
+               >;
+       };
+
+       /* Pointing to IVP HW */
+       uart4_backplane_rif1_pins_default: uart4_backplane_rif1_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0xe8, PIN_INPUT, 8) /* (AG28) PRG0_PRU0_GPO14.UART4_RXD */
+                       J721E_IOPAD(0xec, PIN_OUTPUT, 8) /* (AG27) PRG0_PRU0_GPO15.UART4_TXD */
+               >;
+       };
+
+       /* Pointing to IVP HW */
+       uart6_switch_mgmt_pins_default: uart6_switch_mgmt_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x210, PIN_INPUT, 1) /* (W3) MCAN1_RX.UART6_CTSn */
+                       J721E_IOPAD(0x214, PIN_OUTPUT, 1) /* (V4) MCAN1_TX.UART6_RTSn */
+                       J721E_IOPAD(0x218, PIN_INPUT, 8) /* (W2) I3C0_SCL.UART6_RXD */
+                       J721E_IOPAD(0x21c, PIN_OUTPUT, 8) /* (W1) I3C0_SDA.UART6_TXD */
+               >;
+       };
+
+       /* Pointing to IVP HW */
+       uart7_ftdi_pins_default: uart7_ftdi_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x248, PIN_INPUT, 1) /* (P24) MMC1_DAT1.UART7_CTSn */
+                       J721E_IOPAD(0x24c, PIN_OUTPUT, 1) /* (R24) MMC1_DAT0.UART7_RTSn */
+                       J721E_IOPAD(0x240, PIN_INPUT, 1) /* (R26) MMC1_DAT3.UART7_RXD */
+                       J721E_IOPAD(0x244, PIN_OUTPUT, 1) /* (R25) MMC1_DAT2.UART7_TXD */
+               >;
+       };
+
+       /* Pointing to IVP HW */
+       uart8_backplane_coex71_pins_default: uart8_backplane_coex71_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x124, PIN_INPUT, 14) /* (Y24) PRG0_PRU1_GPO9.UART8_RXD */
+                       J721E_IOPAD(0x128, PIN_OUTPUT, 14) /* (AA25) PRG0_PRU1_GPO10.UART8_TXD */
+               >;
+       };
+
+       /* Pointing to IVP HW */
+       i2c1_msp_pins_default: i2c1_msp_pins_default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
                        J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
                >;
        };
 
-       main_i2c3_pins_default: main-i2c3-pins-default {
+       /* Pointing to IVP HW */
+       i2c3_des_pins_default: i2c3_des_pins_default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
                        J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
                >;
        };
 
-       main_i2c6_pins_default: main-i2c6-pins-default {
+       /* Pointing to IVP HW */
+       i2c4_audio_adc_pins_default: i2c4_audio_adc_pins_default {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
-                       J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
+                       J721E_IOPAD(0x250, PIN_INPUT_PULLUP, 4) /* (P25) MMC1_CLK.I2C4_SCL */
+                       J721E_IOPAD(0x254, PIN_INPUT_PULLUP, 4) /* (R29) MMC1_CMD.I2C4_SDA */
                >;
        };
 
-       mcasp10_pins_default: mcasp10_pins_default {
+       /* Pointing to IVP HW */
+       i2c2_slot7_5_pins_default: i2c2_slot7_5_pins_default {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
-                       J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
-                       J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
-                       J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
-                       J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
-                       J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
-                       J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
-                       J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
-                       J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
+                       J721E_IOPAD(0x1c8, PIN_INPUT_PULLUP, 2) /* (AA1) SPI0_CLK.I2C2_SCL */
+                       J721E_IOPAD(0x1cc, PIN_INPUT_PULLUP, 2) /* (AB5) SPI0_D0.I2C2_SDA */
                >;
        };
 
-       audi_ext_refclk2_pins_default: audi_ext_refclk2_pins_default {
+       /* Pointing to IVP HW */
+       i2c5_avb_clk_pins_default: i2c5_avb_clk_pins_default {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
+                       J721E_IOPAD(0x260, PIN_INPUT_PULLUP, 4) /* (T28) MMC2_DAT3.I2C5_SCL */
+                       J721E_IOPAD(0x264, PIN_INPUT_PULLUP, 4) /* (T29) MMC2_DAT2.I2C5_SDA */
                >;
        };
 
-       main_mmc1_pins_default: main_mmc1_pins_default {
+       /* Pointing to IVP HW */
+       debug_pins_default: debug_pins_default {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
-                       J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
-                       J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
-                       J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
-                       J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
-                       J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
-                       J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
-                       J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
-                       J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
+                       J721E_IOPAD(0x158, PIN_OUTPUT, 5) /* (U23) RGMII5_TX_CTL.TRC_CLK */
+                       J721E_IOPAD(0x15c, PIN_OUTPUT, 5) /* (U26) RGMII5_RX_CTL.TRC_CTL */
+                       J721E_IOPAD(0x28c, PIN_INPUT, 0) /* (V2) TMS */
+                       J721E_IOPAD(0x284, PIN_INPUT, 0) /* (V1) TDI */
+                       J721E_IOPAD(0x288, PIN_OUTPUT, 0) /* (V3) TDO */
+                       J721E_IOPAD(0x160, PIN_OUTPUT, 5) /* (V28) RGMII5_TD3.TRC_DATA0 */
+                       J721E_IOPAD(0x164, PIN_OUTPUT, 5) /* (V29) RGMII5_TD2.TRC_DATA1 */
+                       J721E_IOPAD(0x168, PIN_OUTPUT, 5) /* (V27) RGMII5_TD1.TRC_DATA2 */
+                       J721E_IOPAD(0x16c, PIN_OUTPUT, 5) /* (U28) RGMII5_TD0.TRC_DATA3 */
+                       J721E_IOPAD(0x170, PIN_OUTPUT, 5) /* (U29) RGMII5_TXC.TRC_DATA4 */
+                       J721E_IOPAD(0x174, PIN_OUTPUT, 5) /* (U25) RGMII5_RXC.TRC_DATA5 */
+                       J721E_IOPAD(0x178, PIN_OUTPUT, 5) /* (U27) RGMII5_RD3.TRC_DATA6 */
+                       J721E_IOPAD(0x17c, PIN_OUTPUT, 5) /* (U24) RGMII5_RD2.TRC_DATA7 */
+                       J721E_IOPAD(0x180, PIN_OUTPUT, 5) /* (R23) RGMII5_RD1.TRC_DATA8 */
+                       J721E_IOPAD(0x184, PIN_OUTPUT, 5) /* (T23) RGMII5_RD0.TRC_DATA9 */
+                       J721E_IOPAD(0x188, PIN_OUTPUT, 5) /* (Y28) RGMII6_TX_CTL.TRC_DATA10 */
+                       J721E_IOPAD(0x18c, PIN_OUTPUT, 5) /* (V23) RGMII6_RX_CTL.TRC_DATA11 */
+                       J721E_IOPAD(0x190, PIN_OUTPUT, 5) /* (W23) RGMII6_TD3.TRC_DATA12 */
+                       J721E_IOPAD(0x194, PIN_OUTPUT, 5) /* (W28) RGMII6_TD2.TRC_DATA13 */
+                       J721E_IOPAD(0x198, PIN_OUTPUT, 5) /* (V25) RGMII6_TD1.TRC_DATA14 */
+                       J721E_IOPAD(0x19c, PIN_OUTPUT, 5) /* (W27) RGMII6_TD0.TRC_DATA15 */
+                       J721E_IOPAD(0x1a0, PIN_OUTPUT, 5) /* (W29) RGMII6_TXC.TRC_DATA16 */
+                       J721E_IOPAD(0x1a4, PIN_OUTPUT, 5) /* (W26) RGMII6_RXC.TRC_DATA17 */
+                       J721E_IOPAD(0x1a8, PIN_OUTPUT, 5) /* (Y29) RGMII6_RD3.TRC_DATA18 */
+                       J721E_IOPAD(0x1ac, PIN_OUTPUT, 5) /* (Y27) RGMII6_RD2.TRC_DATA19 */
+                       J721E_IOPAD(0x1b0, PIN_OUTPUT, 5) /* (W24) RGMII6_RD1.TRC_DATA20 */
                >;
        };
 
-       vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
+       /* Pointing to IVP HW */
+       gpio0_pins_default: gpio0_pins_default {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+                       J721E_IOPAD(0x24, PIN_INPUT, 7) /* (AJ20) PRG1_PRU0_GPO8.GPIO0_9 */
+                       J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
+                       J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
+                       J721E_IOPAD(0x4c, PIN_INPUT, 7) /* (AJ21) PRG1_PRU0_GPO17.GPIO0_18 */
+                       J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
+                       J721E_IOPAD(0x7c, PIN_INPUT, 7) /* (AF21) PRG1_PRU1_GPO9.GPIO0_30 */
+                       J721E_IOPAD(0xb0, PIN_INPUT, 7) /* (AF28) PRG0_PRU0_GPO0.GPIO0_43 */
+                       J721E_IOPAD(0xb4, PIN_INPUT, 7) /* (AE28) PRG0_PRU0_GPO1.GPIO0_44 */
+                       J721E_IOPAD(0xe4, PIN_INPUT, 7) /* (AH29) PRG0_PRU0_GPO13.GPIO0_56 */
+                       J721E_IOPAD(0xf0, PIN_INPUT, 7) /* (AH28) PRG0_PRU0_GPO16.GPIO0_59 */
+                       J721E_IOPAD(0x104, PIN_INPUT, 7) /* (AD28) PRG0_PRU1_GPO1.GPIO0_64 */
+                       J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
+                       J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
+                       J721E_IOPAD(0x118, PIN_INPUT, 7) /* (AC26) PRG0_PRU1_GPO6.GPIO0_69 */
+                       J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
+                       J721E_IOPAD(0x140, PIN_INPUT, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */
+                       J721E_IOPAD(0x154, PIN_INPUT, 7) /* (AA27) PRG0_MDIO0_MDC.GPIO0_84 */
+                       J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
+                       J721E_IOPAD(0x1e8, PIN_INPUT, 7) /* (AB2) UART0_RXD.GPIO0_121 */
+                       J721E_IOPAD(0x1f8, PIN_INPUT, 7) /* (AA4) UART1_RXD.GPIO0_125 */
+                       J721E_IOPAD(0x1fc, PIN_INPUT, 7) /* (AB4) UART1_TXD.GPIO0_126 */
                >;
        };
 
-       main_usbss0_pins_default: main_usbss0_pins_default {
+       /* Pointing to IVP HW */
+       gpio1_pins_default: gpio1_pins_default {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
-                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+                       J721E_IOPAD(0x25c, PIN_INPUT, 7) /* (R28) MMC1_SDWP.GPIO1_22 */
+                       J721E_IOPAD(0x268, PIN_INPUT, 7) /* (T27) MMC2_DAT1.GPIO1_25 */
+                       J721E_IOPAD(0x26c, PIN_INPUT, 7) /* (T24) MMC2_DAT0.GPIO1_26 */
+                       J721E_IOPAD(0x290, PIN_INPUT, 7) /* (U6) USB0_DRVVBUS.GPIO1_29 */
+                       J721E_IOPAD(0x294, PIN_INPUT, 7) /* (AD1) MLB0_MLBSP.GPIO1_30 */
+                       J721E_IOPAD(0x298, PIN_INPUT, 7) /* (AC1) MLB0_MLBSN.GPIO1_31 */
                >;
        };
 
-       main_usbss1_pins_default: main_usbss1_pins_default {
+       /* Pointing to IVP HW */
+       mdio_pins_default: mdio_pins_default {
                pinctrl-single,pins = <
-                       J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+                       J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
+                       J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
                >;
        };
-};
 
-&wkup_pmx0 {
-       sw11_button_pins_default: sw11_button_pins_default {
+       /* Pointing to IVP HW */
+       ext_audio_refclk_pins_default: ext_audio_refclk_pins_default {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
+                       J721E_IOPAD(0x1b4, PIN_INPUT, 4) /* (W25) RGMII6_RD0.AUDIO_EXT_REFCLK3 */
+                       J721E_IOPAD(0x278, PIN_OUTPUT, 0) /* (T6) RESETSTATz */
+                       J721E_IOPAD(0x280, PIN_INPUT, 0) /* (U4) SOC_SAFETY_ERRORn */
                >;
        };
 
-       mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+       /* Pointing to IVP HW */
+       can0_faceplate_pins_default: can0_faceplate_pins_default {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
-                       J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
-                       J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
-                       J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
-                       J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
-                       J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
-                       J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
-                       J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
+                       J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
+                       J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
                >;
        };
-};
 
-&wkup_pmx0 {
-       mcu_cpsw_pins_default: mcu_cpsw_pins_default {
+       /* Pointing to IVP HW */
+       can6_faceplate_pins_default: can6_faceplate_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x44, PIN_INPUT, 6) /* (AE24) PRG1_PRU0_GPO16.MCAN6_RX */
+                       J721E_IOPAD(0x40, PIN_OUTPUT, 6) /* (AC24) PRG1_PRU0_GPO15.MCAN6_TX */
+               >;
+       };
+
+       mcasp0_tuner_deserializer_pins_default: mcasp0_tuner_deserializer_pins_default {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
-                       J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
-                       J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
-                       J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
-                       J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
-                       J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
-                       J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
-                       J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
-                       J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
-                       J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
-                       J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
-                       J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
+                       J721E_IOPAD(0xd4, PIN_INPUT, 12) /* (AB26) PRG0_PRU0_GPO9.MCASP0_ACLKX */
+                       J721E_IOPAD(0xd8, PIN_INPUT, 12) /* (AB25) PRG0_PRU0_GPO10.MCASP0_AFSX */
+                       J721E_IOPAD(0xf8, PIN_INPUT, 12) /* (AB29) PRG0_PRU0_GPO18.MCASP0_AXR14 */
+                       J721E_IOPAD(0xfc, PIN_INPUT, 12) /* (AB28) PRG0_PRU0_GPO19.MCASP0_AXR15 */
+                       J721E_IOPAD(0xc0, PIN_INPUT, 12) /* (AD25) PRG0_PRU0_GPO4.MCASP0_AXR2 */
+                       J721E_IOPAD(0xc8, PIN_INPUT, 12) /* (AE26) PRG0_PRU0_GPO6.MCASP0_AXR4 */
+                       J721E_IOPAD(0xcc, PIN_INPUT, 12) /* (AC28) PRG0_PRU0_GPO7.MCASP0_AXR5 */
+                       J721E_IOPAD(0xd0, PIN_INPUT, 12) /* (AC27) PRG0_PRU0_GPO8.MCASP0_AXR6 */
                >;
        };
+};
 
-       mcu_mdio_pins_default: mcu_mdio1_pins_default {
+&main_mcan0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&can0_faceplate_pins_default>;
+       stb-gpios = <&main_gpio0 84 GPIO_ACTIVE_HIGH>;
+       can-transceiver {
+               max-bitrate = <5000000>;
+       };
+};
+
+&main_mcan6 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&can6_faceplate_pins_default>;
+       stb-gpios = <&main_gpio0 125 GPIO_ACTIVE_HIGH>;
+       can-transceiver {
+               max-bitrate = <5000000>;
+       };
+};
+
+&wkup_pmx0 {
+       sw11_button_pins_default: sw11_button_pins_default {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
-                       J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
+                       J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
                >;
        };
+};
+
+&wkup_pmx0 {
 
-       mcu_mcan0_pins_default: mcu-mcan0-pins-default {
+       /* Pointing to IVP HW */
+       mywkup_debug_pins_default: mywkup_debug_pins_default {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
-                       J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
+                       J721E_WKUP_IOPAD(0x128, PIN_INPUT, 0) /* (C26) EMU0 */
+                       J721E_WKUP_IOPAD(0x12c, PIN_INPUT, 0) /* (B29) EMU1 */
+                       J721E_WKUP_IOPAD(0x120, PIN_INPUT, 0) /* (E29) TCK */
+                       J721E_WKUP_IOPAD(0x124, PIN_INPUT, 0) /* (F24) TRSTn */
                >;
        };
 
-       mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
+       /* Pointing to IVP HW */
+       wkup_gpio_pins_default: wkup_gpio_pins_default {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
-                       J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
+                       J721E_WKUP_IOPAD(0x4, PIN_INPUT, 7) /* (C21) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */
                >;
        };
 
-       mcu_mcan1_pins_default: mcu-mcan1-pins-default {
+       /* Pointing to IVP HW */
+       wkup_system_pins_default: wkup_system_pins_default {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
-                       J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
+                       J721E_WKUP_IOPAD(0x11c, PIN_OUTPUT, 0) /* (B28) MCU_PORz_OUT */
+                       J721E_WKUP_IOPAD(0x118, PIN_OUTPUT, 0) /* (C27) MCU_RESETSTATz */
+                       J721E_WKUP_IOPAD(0x114, PIN_INPUT, 0) /* (D28) MCU_RESETz */
+                       J721E_WKUP_IOPAD(0x110, PIN_INPUT, 0) /* (D27) MCU_SAFETY_ERRORn */
+                       J721E_WKUP_IOPAD(0x10c, PIN_OUTPUT, 0) /* (G23) PMIC_POWER_EN1 */
+                       J721E_WKUP_IOPAD(0x174, PIN_INPUT, 0) /* (J24) PORz */
+                       J721E_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (C28) RESET_REQz */
                >;
        };
 
-       mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
+       /* Pointing to IVP HW */
+       mcasp3_audio_adc_pins_default: mcasp3_audio_adc_pins_default {
                pinctrl-single,pins = <
-                       J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
+                       J721E_IOPAD(0x28, PIN_INPUT, 12) /* (AG20) PRG1_PRU0_GPO9.MCASP3_ACLKX */
+                       J721E_IOPAD(0x2c, PIN_INPUT, 12) /* (AD21) PRG1_PRU0_GPO10.MCASP3_AFSX */
+                       J721E_IOPAD(0x20, PIN_INPUT, 12) /* (AE20) PRG1_PRU0_GPO7.MCASP3_AXR1 */
                >;
        };
 };
@@ -343,13 +505,44 @@
        status = "disabled";
 };
 
+/* Pointing to IVP HW */
 &main_uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_backplane_coex61_pins_default>;
        power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+       status = "okay";
 };
 
+/* Pointing to IVP HW */
+&main_uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_backplane_coex60_pins_default>;
+       power-domains = <&k3_pds 278 TI_SCI_PD_SHARED>;
+       status = "okay";
+};
+
+/* Pointing to IVP HW */
+&main_uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart2_bckplane_coex70_pins_default>;
+       power-domains = <&k3_pds 279 TI_SCI_PD_SHARED>;
+       status = "okay";
+};
+
+/* Pointing to IVP HW */
 &main_uart3 {
-       /* UART not brought out */
-       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart3_backplane_rif0_pins_default>;
+       power-domains = <&k3_pds 280 TI_SCI_PD_SHARED>;
+       status = "okay";
+};
+
+/* Pointing to IVP HW */
+&main_uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart4_backplane_rif1_pins_default>;
+       power-domains = <&k3_pds 281 TI_SCI_PD_SHARED>;
+       status = "okay";
 };
 
 &main_uart5 {
@@ -358,18 +551,27 @@
 };
 
 &main_uart6 {
-       /* UART not brought out */
-       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart6_switch_mgmt_pins_default>;
+       current-speed = <230400>;
+       power-domains = <&k3_pds 283 TI_SCI_PD_SHARED>;
+       
+       status = "okay";
 };
 
+
 &main_uart7 {
-       /* UART not brought out */
-       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart7_ftdi_pins_default>;
+       power-domains = <&k3_pds 284 TI_SCI_PD_SHARED>;
+       status = "okay";
 };
 
 &main_uart8 {
-       /* UART not brought out */
-       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart8_backplane_coex71_pins_default>;
+       power-domains = <&k3_pds 285 TI_SCI_PD_SHARED>;
+       status = "okay";
 };
 
 &main_uart9 {
@@ -534,25 +736,6 @@
        mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
 };
 
-&ospi1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
-
-       flash@0{
-               compatible = "jedec,spi-nor";
-               reg = <0x0>;
-               spi-tx-bus-width = <1>;
-               spi-rx-bus-width = <4>;
-               spi-max-frequency = <40000000>;
-               cdns,tshsl-ns = <60>;
-               cdns,tsd2d-ns = <60>;
-               cdns,tchsh-ns = <60>;
-               cdns,tslch-ns = <60>;
-               cdns,read-delay = <2>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-       };
-};
 
 &tscadc0 {
        adc {
@@ -646,7 +829,7 @@
 
 &main_i2c1 {
        pinctrl-names = "default";
-       pinctrl-0 = <&main_i2c1_pins_default>;
+       pinctrl-0 = <&i2c1_msp_pins_default>;
        clock-frequency = <400000>;
 
        exp4: gpio@20 {
@@ -674,7 +857,7 @@
 &k3_clks {
        /* Confiure AUDIO_EXT_REFCLK2 pin as output */
        pinctrl-names = "default";
-       pinctrl-0 = <&audi_ext_refclk2_pins_default>;
+       pinctrl-0 = <&ext_audio_refclk_pins_default>;
 };
 
 &main_i2c3 {
@@ -728,44 +911,36 @@
        };
 };
 
-&mcasp10 {
-       #sound-dai-cells = <0>;
-
+&main_i2c2 {
        pinctrl-names = "default";
-       pinctrl-0 = <&mcasp10_pins_default>;
+       pinctrl-0 = <&i2c2_slot7_5_pins_default>;
+       clock-frequency = <400000>;
 
-       op-mode = <0>;          /* MCASP_IIS_MODE */
-       tdm-slots = <2>;
-       auxclk-fs-ratio = <256>;
+};
 
-       serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
-               1 1 1 1
-               2 2 2 0
-       >;
-       tx-num-evt = <0>;
-       rx-num-evt = <0>;
+&main_i2c3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c3_des_pins_default>;
+       clock-frequency = <400000>;
 
-       status = "okay";
 };
 
-&mcu_cpsw {
+&main_i2c4 {
        pinctrl-names = "default";
-       pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
-};
+       pinctrl-0 = <&i2c4_audio_adc_pins_default>;
+       clock-frequency = <400000>;
 
-&davinci_mdio {
-       phy0: ethernet-phy@0 {
-               reg = <0>;
-               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-       };
 };
 
-&cpsw_port1 {
-       phy-mode = "rgmii-rxid";
-       phy-handle = <&phy0>;
+/* Pointing to IVP HW */
+&main_i2c5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c5_avb_clk_pins_default>;
+       status = "okay";
+       power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>;
 };
 
+
 &main_sdhci0 {
        /* eMMC */
        non-removable;
@@ -775,11 +950,7 @@
 
 &main_sdhci1 {
        /* SD/MMC */
-       vmmc-supply = <&vdd_mmc1>;
-       vqmmc-supply = <&vdd_sd_dv_alt>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_mmc1_pins_default>;
-       disable-wp;
+       status = "disabled";
 };
 
 &main_sdhci2 {
@@ -787,6 +958,30 @@
        status = "disabled";
 };
 
+&wiz2_pll1_refclk {
+       assigned-clock-parents = <&dummy_cmn_refclk1>;
+};
+
+&wiz2_refclk_dig {
+       assigned-clock-parents = <&dummy_cmn_refclk1>;
+};
+
+&serdes2_pll_cmnlc {
+       assigned-clock-parents = <&serdes2_refrcv1>;
+};
+
+&wiz3_pll1_refclk {
+       assigned-clock-parents = <&dummy_cmn_refclk1>;
+};
+
+&wiz3_refclk_dig {
+       assigned-clock-parents = <&dummy_cmn_refclk1>;
+};
+
+&serdes3_pll_cmnlc {
+       assigned-clock-parents = <&serdes3_refrcv1>;
+};
+
 &serdes0 {
        serdes0_pcie_link: link@0 {
                reg = <0>;
@@ -794,6 +989,7 @@
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
                resets = <&serdes_wiz0 1>;
+               status = "disabled";
        };
 };
 
@@ -804,6 +1000,7 @@
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
                resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+               status = "disabled";
        };
 };
 
@@ -818,37 +1015,32 @@
 };
 
 &pcie0_rc {
-       reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
-       phys = <&serdes0_pcie_link>;
-       phy-names = "pcie_phy";
-       num-lanes = <1>;
+       status = "disabled";
 };
 
 &pcie1_rc {
-       reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
-       phys = <&serdes1_pcie_link>;
-       phy-names = "pcie_phy";
-       num-lanes = <2>;
+       status = "disabled";
 };
 
 &pcie2_rc {
-       reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
        phys = <&serdes2_pcie_link>;
        phy-names = "pcie_phy";
        num-lanes = <2>;
 };
 
+&pcie3_rc {
+    reset-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>;
+    phys = <&serdes3_pcie_link>;
+    phy-names = "pcie_phy";
+    num-lanes = <2>;
+};
+
 &pcie0_ep {
-       phys = <&serdes0_pcie_link>;
-       phy-names = "pcie_phy";
-       num-lanes = <1>;
        status = "disabled";
 };
 
 &pcie1_ep {
-       phys = <&serdes1_pcie_link>;
-       phy-names = "pcie_phy";
-       num-lanes = <2>;
        status = "disabled";
 };
 
@@ -859,57 +1051,49 @@
        status = "disabled";
 };
 
-&pcie3_rc {
-       status = "disabled";
-};
-
 &pcie3_ep {
        status = "disabled";
 };
 
-&usb_serdes_mux {
-       idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
-};
-
 &serdes_ln_ctrl {
-       idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
-                     <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
-                     <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-                     <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
-                     <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
-};
-
-&serdes_wiz3 {
-       typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
-       typec-dir-debounce-ms = <700>;  /* TUSB321, tCCB_DEFAULT 133 ms */
+       idle-states = <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+                     <SERDES3_LANE0_PCIE3_LANE0>, <SERDES3_LANE1_PCIE3_LANE1>;
 };
 
 &serdes3 {
-       serdes3_usb_link: link@0 {
+       serdes3_pcie_link: link@0 {
                reg = <0>;
                cdns,num-lanes = <2>;
                #phy-cells = <0>;
-               cdns,phy-type = <PHY_TYPE_USB3>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
                resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
        };
 };
 
+&serdes_wiz0 {
+       status = "disabled";
+};
+
+&serdes_wiz1 {
+       status = "disabled";
+};
+
+&serdes_wiz4 {
+       status = "disabled";
+};
+
+
 &usbss0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_usbss0_pins_default>;
        ti,vbus-divider;
+       ti,usb2-only;
 };
 
 &usb0 {
-       dr_mode = "otg";
-       maximum-speed = "super-speed";
-       phys = <&serdes3_usb_link>;
-       phy-names = "cdns3,usb3-phy";
+       dr_mode = "host";
+       maximum-speed = "high-speed";
 };
 
 &usbss1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_usbss1_pins_default>;
        ti,usb2-only;
 };
 
@@ -918,36 +1102,61 @@
        maximum-speed = "high-speed";
 };
 
-/* uart2 assigned to cpsw9g eth-switch fw running on remote CPU core */
-&main_uart2 {
-       status = "disabled";
-};
 
-&mcu_mcan0 {
+/* Pointing to IVP HW */
+&main_gpio0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&gpio0_pins_default &debug_pins_default>;
+       power-domains = <&k3_pds 105 TI_SCI_PD_SHARED>;
        status = "okay";
+};
+
+/* Pointing to IVP HW */
+&main_gpio1 {
        pinctrl-names = "default";
-       pinctrl-0 = <&mcu_mcan0_pins_default &mcu_mcan0_gpio_pins_default>;
-       stb-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_HIGH>;
-       en-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
-       can-transceiver {
-               max-bitrate = <5000000>;
-       };
+       pinctrl-0 = <&gpio1_pins_default>;
+       power-domains = <&k3_pds 106 TI_SCI_PD_SHARED>;
+       status = "okay";
 };
 
-&mcu_mcan1 {
+/* Pointing to IVP HW */
+&wkup_gpio0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&wkup_gpio_pins_default &mywkup_debug_pins_default &wkup_system_pins_default>;
+       power-domains = <&k3_pds 113 TI_SCI_PD_SHARED>;
        status = "okay";
+};
+
+&mcasp0 {
+       #sound-dai-cells = <0>;
+
        pinctrl-names = "default";
-       pinctrl-0 = <&mcu_mcan1_pins_default &mcu_mcan1_gpio_pins_default>;
-       stb-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_LOW>;
-       can-transceiver {
-               max-bitrate = <5000000>;
-       };
+       pinctrl-0 = <&mcasp0_tuner_deserializer_pins_default>;
+
+       op-mode = <0>;          /* MCASP_IIS_MODE */
+       tdm-slots = <2>;
+       auxclk-fs-ratio = <256>;
+
+       serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+               1 1 1 1
+               2 2 2 1
+               1 1 1 2
+               2 2 0 0
+       >;
+       tx-num-evt = <0>;
+       rx-num-evt = <0>;
+
+       status = "okay";
 };
 
-&main_mcan0 {
-       status = "disabled";
+&mcasp3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcasp3_audio_adc_pins_default>;
+       power-domains = <&k3_pds 177 TI_SCI_PD_SHARED>;
+       status = "okay";
 };
 
+
 &main_mcan1 {
        status = "disabled";
 };
@@ -968,10 +1177,6 @@
        status = "disabled";
 };
 
-&main_mcan6 {
-       status = "disabled";
-};
-
 &main_mcan7 {
        status = "disabled";
 };

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 8675a4887cab..70651bbd6a64 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -53,17 +53,12 @@
                serdes_ln_ctrl: serdes_ln_ctrl@4080 {
                        compatible = "mmio-mux";
                        #mux-control-cells = <1>;
-                       mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
-                                       <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
-                                       <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
-                                       <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
-                                       <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+                       mux-reg-masks = <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+                                       <0x40b0 0x3>, <0x40b4 0x3>; /* SERDES3 lane0/1 select */
+                                       
                                        /* SERDES4 lane0/1/2/3 select */
-                       idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
-                                     <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
-                                     <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-                                     <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
-                                     <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+                       idle-states = <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+                                     <SERDES3_LANE0_PCIE3_LANE0>, <SERDES3_LANE1_PCIE3_LANE1>;
                };
 
                usb_serdes_mux: mux-controller@4000 {
@@ -412,13 +407,13 @@
        dummy_cmn_refclk: dummy_cmn_refclk {
                #clock-cells = <0>;
                compatible = "fixed-clock";
-               clock-frequency = <0>;
+               clock-frequency = <100000000>;
        };
 
        dummy_cmn_refclk1: dummy_cmn_refclk1 {
                #clock-cells = <0>;
                compatible = "fixed-clock";
-               clock-frequency = <0>;
+               clock-frequency = <100000000>;
        };
 
        serdes_wiz0: wiz@5000000 {
@@ -473,8 +468,36 @@
                        #size-cells = <0>;
                        resets = <&serdes_wiz0 0>;
                        reset-names = "sierra_reset";
-                       clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
-                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+                       clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&serdes0_pll_cmnlc>, <&serdes0_pll_cmnlc1>;
+                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+                       serdes0_refrcv: refrcv {
+                               clocks = <&wiz0_pll0_refclk>;
+                               clock-names = "pll_refclk";
+                               #clock-cells = <0>;
+                       };
+
+                       serdes0_refrcv1: refrcv1 {
+                               clocks = <&wiz0_pll1_refclk>;
+                               clock-names = "pll_refclk";
+                               #clock-cells = <0>;
+                       };
+
+                       serdes0_pll_cmnlc: pll_cmnlc {
+                               clocks = <&wiz0_pll0_refclk>, <&serdes0_refrcv1>;
+                               clock-names = "pll_refclk", "refrcv";
+                               #clock-cells = <0>;
+                               assigned-clocks = <&serdes0_pll_cmnlc>;
+                               assigned-clock-parents = <&wiz0_pll0_refclk>;
+                       };
+
+                       serdes0_pll_cmnlc1: pll_cmnlc1 {
+                               clocks = <&wiz0_pll1_refclk>, <&serdes0_refrcv>;
+                               clock-names = "pll_refclk", "refrcv";
+                               #clock-cells = <0>;
+                               assigned-clocks = <&serdes0_pll_cmnlc1>;
+                               assigned-clock-parents = <&wiz0_pll1_refclk>;
+                       };
                };
        };
 
@@ -530,8 +553,36 @@
                        #size-cells = <0>;
                        resets = <&serdes_wiz1 0>;
                        reset-names = "sierra_reset";
-                       clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
-                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+                       clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&serdes1_pll_cmnlc>, <&serdes1_pll_cmnlc1>;
+                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+                       serdes1_refrcv: refrcv {
+                               clocks = <&wiz1_pll0_refclk>;
+                               clock-names = "pll_refclk";
+                               #clock-cells = <0>;
+                       };
+
+                       serdes1_refrcv1: refrcv1 {
+                               clocks = <&wiz1_pll1_refclk>;
+                               clock-names = "pll_refclk";
+                               #clock-cells = <0>;
+                       };
+
+                       serdes1_pll_cmnlc: pll_cmnlc {
+                               clocks = <&wiz1_pll0_refclk>, <&serdes1_refrcv1>;
+                               clock-names = "pll_refclk", "refrcv";
+                               #clock-cells = <0>;
+                               assigned-clocks = <&serdes1_pll_cmnlc>;
+                               assigned-clock-parents = <&wiz1_pll0_refclk>;
+                       };
+
+                       serdes1_pll_cmnlc1: pll_cmnlc1 {
+                               clocks = <&wiz1_pll1_refclk>, <&serdes1_refrcv>;
+                               clock-names = "pll_refclk", "refrcv";
+                               #clock-cells = <0>;
+                               assigned-clocks = <&serdes1_pll_cmnlc1>;
+                               assigned-clock-parents = <&wiz1_pll1_refclk>;
+                       };
                };
        };
 
@@ -587,8 +638,36 @@
                        #size-cells = <0>;
                        resets = <&serdes_wiz2 0>;
                        reset-names = "sierra_reset";
-                       clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
-                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+                       clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&serdes2_pll_cmnlc>, <&serdes2_pll_cmnlc1>;
+                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+                       serdes2_refrcv: refrcv {
+                               clocks = <&wiz2_pll0_refclk>;
+                               clock-names = "pll_refclk";
+                               #clock-cells = <0>;
+                       };
+
+                       serdes2_refrcv1: refrcv1 {
+                               clocks = <&wiz2_pll1_refclk>;
+                               clock-names = "pll_refclk";
+                               #clock-cells = <0>;
+                       };
+
+                       serdes2_pll_cmnlc: pll_cmnlc {
+                               clocks = <&wiz2_pll0_refclk>, <&serdes2_refrcv1>;
+                               clock-names = "pll_refclk", "refrcv";
+                               #clock-cells = <0>;
+                               assigned-clocks = <&serdes2_pll_cmnlc>;
+                               assigned-clock-parents = <&wiz2_pll0_refclk>;
+                       };
+
+                       serdes2_pll_cmnlc1: pll_cmnlc1 {
+                               clocks = <&wiz2_pll1_refclk>, <&serdes2_refrcv>;
+                               clock-names = "pll_refclk", "refrcv";
+                               #clock-cells = <0>;
+                               assigned-clocks = <&serdes2_pll_cmnlc1>;
+                               assigned-clock-parents = <&wiz2_pll1_refclk>;
+                       };
                };
        };
 
@@ -644,8 +723,36 @@
                        #size-cells = <0>;
                        resets = <&serdes_wiz3 0>;
                        reset-names = "sierra_reset";
-                       clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
-                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+                       clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div> , <&serdes3_pll_cmnlc> , <&serdes3_pll_cmnlc1>;
+                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+                       serdes3_refrcv: refrcv {
+                               clocks = <&wiz3_pll0_refclk>;
+                               clock-names = "pll_refclk";
+                               #clock-cells = <0>;
+                       };
+
+                       serdes3_refrcv1: refrcv1 {
+                               clocks = <&wiz3_pll1_refclk>;
+                               clock-names = "pll_refclk";
+                               #clock-cells = <0>;
+                       };
+
+                       serdes3_pll_cmnlc: pll_cmnlc {
+                               clocks = <&wiz3_pll0_refclk>, <&serdes3_refrcv1>;
+                               clock-names = "pll_refclk", "refrcv";
+                               #clock-cells = <0>;
+                               assigned-clocks = <&serdes3_pll_cmnlc>;
+                               assigned-clock-parents = <&wiz3_pll0_refclk>;
+                       };
+
+                       serdes3_pll_cmnlc1: pll_cmnlc1 {
+                               clocks = <&wiz3_pll1_refclk>, <&serdes3_refrcv>;
+                               clock-names = "pll_refclk", "refrcv";
+                               #clock-cells = <0>;
+                               assigned-clocks = <&serdes3_pll_cmnlc1>;
+                               assigned-clock-parents = <&wiz3_pll1_refclk>;
+                       };
                };
        };
 

diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 8c19acc26902..77a7baefaa62 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -30,7 +30,6 @@
                serial9 = &main_uart7;
                serial10 = &main_uart8;
                serial11 = &main_uart9;
-               ethernet0 = &cpsw_port1;
                rproc0 = &mcu_r5fss0_core0;
                rproc1 = &mcu_r5fss0_core1;
                rproc2 = &main_r5fss0_core0;

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts b/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
index 020b6e44e061..e0e9c8e8ce75 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dts
@@ -9,7 +9,7 @@
 
 &wkup_i2c0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&wkup_i2c0_pins_default>;
+       pinctrl-0 = <&wkup_i2c0_pmic_pins_default>;
        clock-frequency = <400000>;
 
        tps65917: tps65917@58 {
@@ -44,23 +44,3 @@
        };
 };
 
-&mcasp10_pins_default {
-       pinctrl-single,pins = <
-               J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
-               J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
-               J721E_IOPAD(0x160, PIN_INPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
-               J721E_IOPAD(0x164, PIN_INPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
-               J721E_IOPAD(0x170, PIN_INPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
-               J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
-               J721E_IOPAD(0x198, PIN_OUTPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
-               J721E_IOPAD(0x19c, PIN_OUTPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
-               J721E_IOPAD(0x1a0, PIN_OUTPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
-       >;
-};
-
-&mcasp10 {
-       serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
-               2 2 2 1
-               1 1 1 0
-       >;
-};

Thanks,

Satish

Satish,

It's not clear to me what the question is. Could you elaborate more on "I made the following device tree changes but I don't see any mcasp3 port for communication?"

I see you have added a mcasp3 dts node, and I'm sure you also have one more node for the PCM6260 ADC. But you will also need a sound node that glues McASP3 and PCM6260 together. Have a look at k3-j721e-common-proc-board-infotainment.dtso for an example.

Now, the *infotainment.dtso file is for a multi-codec case. Your connection is simpler as you don't have multiple audio codecs, just one ADC. ALSA SoC has a simple-card feature that provides a generic driver for simple connections where you have only one CPU DAI (i.e. McASP3) and single codec (i.e. PCM6260 ADC). I think that could work for you.

-Misa

Hi Misa,

Thank you for the suggestion of adding a sound node. That is missing in my code. Let me test by adding it and I will return here.

Thanks,

Satish

Hi Misa,

Today I looked on k3-j721e-common-proc-board-infotainment.dtso and got a little more confused. 

A sound node in k3-j721e-common-proc-board.dts looked more simple to me and I started following it.

	sound0: sound@0 {
		compatible = "ti,j721e-cpb-audio";
		ti,model = "j721e-cpb-analog";

		ti,cpb-mcasp = <&mcasp3>;
		ti,cpb-codec = <&pcm3168a_1>;

		clocks = <&pll4>, <&pll15>,
			 <&k3_clks 184 1>,
			 <&k3_clks 184 2>, <&k3_clks 184 4>,
			 <&k3_clks 157 371>,
			 <&k3_clks 157 400>, <&k3_clks 157 401>;
		clock-names = "pll4", "pll15",
			      "cpb-mcasp",
			      "cpb-mcasp-48000", "cpb-mcasp-44100",
			      "audio-refclk2",
			      "audio-refclk2-48000", "audio-refclk2-44100";
	};

In this node -

Does "compatible" & "ti,model" entry looks good to you?

As you mentioned that I need a node for PCM6260 ADC. This is also missing in my device tree. Where Can I find it?

Thanks,

Satish 

Satish,

j721e-cpb-audio is not the right type for your sound card. It's used to enable a type of connection where a single McASP is connected to two different audio codecs (I think using TDM).

Your McASP - PCM6260 connection is a basic kind of connection and the ASoC's "simple card" driver is the right choice here, IMO.

In order to get familiar with ASoC, I'd recommend going through kernel's documentation (see here). It will give you a big picture view of how sound cards are enabled, what the building blocks are, etc.

Take a look at the devicetree binding info of the "simple card" here. It shows what properties that node supports, examples, etc.

Finally, to see if PCM6260 ADC is supported in kernel, please check in <kernel>/sound/soc/codecs/ to see if there is an existing driver for that ADC. I don't see a driver for that ADC in the kernel which I have handy (it's a bit old kernel version).

-Misa

Hi Misa,

I will take a look on ASoC documentation and DT. Thank you for sharing those links. Meantime I checked <kernel>/sound/soc/codecs/ but didn't find the Device driver for PCM6260 ADC. 

Meantime, it would be great to find out from Linux SDK team to see if they have any plan for developing a driver for it or this is something we have to develop?

Thanks,

Satish

Satish, 

In an earlier conversation I had with Misa, he noted that to me that driver support for PCM6260 does not exist and if needed this will be something that you have to develop.  

John

Hi Misa

I have been trying to add minimum DT entries to get the sound card detected as the first step.  I have tested with the following three DT entries but I don't see a sound card detected in my case. This is the error I get -

root@j7-evm:~# dmesg | grep sound
[    3.738866]   No soundcards found.
[    9.185405] asoc-simple-card: probe of sound@0 failed with error -22

These DT entries have been tested individually (meaning one node at one time, not all three)

My question is -

What is the minimum DT entries required to detect the sound card?

Does "simple-audio-card,name = "AM65x-GPEVM";" entry looks correct to you?

	sound0: sound@0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "AM65x-GPEVM";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",	"HPLOUT",
			"Headphone Jack",	"HPROUT",
			"LINE1L",		"Line In",
			"LINE1R",		"Line In";
		simple-audio-card,format = "i2s";
	};
	
	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "AM65x-GPEVM";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",	"HPLOUT",
			"Headphone Jack",	"HPROUT",
			"LINE1L",		"Line In",
			"LINE1R",		"Line In";
		simple-audio-card,format = "i2s";

		simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
		};
	};
	
	
	sound{
		compatible = "simple-audio-card";
	};
	
	

Thanks,

Satish

Satish,

Your sound0 node is missing the handles to the CODEC and CPU DAI. If you use the "Example 1" of the simple card devicetree documentation, you are missing the "simple-audio-card,cpu" and "simple-audio-card,codec" elements:

	simple-audio-card,cpu {
		sound-dai = <&sh_fsi2 0>;
	};

	dailink0_master: simple-audio-card,codec {
		sound-dai = <&ak4648>;
		clocks = <&osc>;
	};

I'm not sure what the two "sound" nodes are meant for, but shouldn't need them.

Satish Lal Das2 said:

Does "simple-audio-card,name = "AM65x-GPEVM";" entry looks correct to you?

Yes, card name can be any string.

-Misa

Thank you Misa!

It looks like now we are able to detect the sound card 

root@j7-evm:~# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: AM65xGPEVM [AM65x-GPEVM], device 0: davinci-mcasp.0-davinci-mcasp.0 2b30000.mcasp-0 [davinci-mcasp.0-davinci-mcasp.0 2b30000.mcasp-0]
Subdevices: 1/1
Subdevice #0: subdevice #0
root@j7-evm:~#

I am keeping this E2E open for now until I complete my testing on our hardware.

Thank you again,

Satish

Hi Misa,

on Mcasp DT example node :  https://github.com/CumulusNetworks/linux-apd/blob/master/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt 

Do you know the meaning of "tx-num-evt" & "rx-num-evt"?

tx-num-evt : FIFO levels

rx-num-evt : FIFO levels 

I have set them 1 & 1 in my DT setting for Mcasp3 which is used for this ADC. However, I am not sure if I need them or setting them with 1 is correct or now.

It's the McASP FIFO threshold. For example, for RX, it's the number of elements in the entries in the FIFO that should be filled for DMA to read data from the FIFO.

Setting them to 1 is correct.