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not work ddr2 and с6457

Vladimir Solodky
Intellectual 550 points
Other Parts Discussed in Thread: TMS320C6457

Doesn't work DDR2 (2 chips MT47H128M16HG-3IT:A) c c6457.
Подлючено under the scheme sprugk5c.pdf page 30 (Figure 16).

Program code:

/////////////////////////////File ddr2.h

#ifndef DDR2_DEFH

#define DDR2_DEFH

#define MIDRDDR2 ((volatile unsigned int *)0x78000000)
#define DMCSTAT ((volatile unsigned int *)0x78000004)
#define SDCFG ((volatile unsigned int *)0x78000008)
#define SDRFC ((volatile unsigned int *)0x7800000C)
#define SDTIM1 ((volatile unsigned int *)0x78000010)
#define SDTIM2 ((volatile unsigned int *)0x78000014)
#define BPRIO ((volatile unsigned int *)0x78000020)
#define DMCCTL ((volatile unsigned int *)0x780000E4)

typedef struct // SIZE = 4 byte
{
unsigned int PAGESIZE : 3;
unsigned int RES1 : 1;
unsigned int IBANK : 3;
unsigned int RES2 : 2;
unsigned int CL : 3;
unsigned int RES3 : 2;
unsigned int NM : 1;
unsigned int TIMUNLOCK : 1;
unsigned int SDRAM_ENABLE : 1;
unsigned int DDR_ENABLE : 1;
unsigned int SDRAM_DRIVE0 : 1;
unsigned int DDR_DISABLE_DLL : 1;
unsigned int DDR2_ENABLE : 1;
unsigned int DDR2_TERM0 : 1;
unsigned int DDR2_DDQS : 1;
unsigned int BOOT_UNLOCK : 1;
unsigned int RES4 : 3;
unsigned int DDR2_TERM1 : 1;
unsigned int RES5 : 4;
} SDCFG_struct;

typedef struct // SIZE = 4 byte
{
unsigned int REFRESH_RATE : 16;
unsigned int RES1 : 15;
unsigned int SR : 1;
} SDRFC_struct;

typedef struct // SIZE = 4 byte
{
unsigned int T_WTR : 2;
unsigned int RES1 : 1;
unsigned int T_RRD : 3;
unsigned int T_RC : 5;
unsigned int T_RAS : 5;
unsigned int T_WR : 3;
unsigned int T_RCD : 3;
unsigned int T_RP : 3;
unsigned int T_RFC : 7;
} SDTIM1_struct;

typedef struct // SIZE = 4 byte
{
unsigned int T_CKE : 5;
unsigned int T_RTP : 3;
unsigned int T_XSRD : 8;
unsigned int T_XSNR : 7;
unsigned int T_ODT : 2;
unsigned int RES1 : 7;
} SDTIM2_struct;

typedef struct // SIZE = 4 byte
{
unsigned int RL : 3;
unsigned int RES1 : 1;
unsigned int DDRPVTCNTL : 2;
unsigned int RES2 : 3;
unsigned int DDRSLRATE : 1;
unsigned int RES3 : 22;
} DMCCTL_struct;

#endif

 

/////////////////////////program

SDCFG_struct ddr2cfg;
SDRFC_struct ddr2rfc;
SDTIM1_struct ddr2tim1;
SDTIM2_struct ddr2tim2;
DMCCTL_struct ddr2ctl;

#define DDR2CLKOUT 250.0 //208.333
#define REFRESHRATE 3.9 // usec

#define TWTR 7.5 // ns
#define TRRD 7.5 // ns
#define TRC 55.0 // ns
#define TRAS 40.0 // ns
#define TWR 15.0 // ns
#define TRCD 15.0 // ns
#define TRP 15.0 // ns
#define TRFC 195.0 // ns

#define TCKE 3.0
#define TRTP 7.5 // ns
#define TXSRD 200.0
#define TXSNR 210.0 // ns
#define TODT 2

*((int*)(&ddr2cfg)) = *SDCFG;
*((int*)(&ddr2rfc)) = *SDRFC;
*((int*)(&ddr2tim1)) = *SDTIM1;
*((int*)(&ddr2tim2)) = *SDTIM2;
*((int*)(&ddr2ctl)) = *DMCCTL;

ddr2cfg.TIMUNLOCK = 1;
ddr2cfg.BOOT_UNLOCK = 1;
*SDCFG = *((int*)(&ddr2cfg));

ddr2cfg.PAGESIZE = 2; // 1024 word
ddr2cfg.IBANK = 3; // 8 banks
ddr2cfg.CL = 5; // CL
ddr2cfg.NM = 0; // 32 bit
ddr2cfg.TIMUNLOCK = 1; // UnLock
ddr2cfg.SDRAM_ENABLE = 1; // Enable SDRAM
ddr2cfg.DDR_ENABLE = 1; // Enable DDR
ddr2cfg.SDRAM_DRIVE0 = 0; // Normal
ddr2cfg.DDR_DISABLE_DLL = 0; // Enable DDR DLL
ddr2cfg.DDR2_ENABLE = 1; // DDR2 Enable
ddr2cfg.DDR2_TERM0 = 1; // 50 Om
ddr2cfg.DDR2_DDQS = 1; //
ddr2cfg.BOOT_UNLOCK = 1; // UnLock
ddr2cfg.DDR2_TERM1 = 1; // 50 Om
*SDCFG = *((int*)(&ddr2cfg));

ddr2tim1.T_WTR = ceil(TWTR * DDR2CLKOUT/1000.0 - 1);
ddr2tim1.T_RRD = ceil(TRRD * DDR2CLKOUT/1000.0 - 0.5);
ddr2tim1.T_RC = ceil(TRC * DDR2CLKOUT/1000.0 - 1);
ddr2tim1.T_RAS = ceil(TRAS * DDR2CLKOUT/1000.0 - 1);
ddr2tim1.T_WR = ceil(TWR * DDR2CLKOUT/1000.0 - 1);
ddr2tim1.T_RCD = ceil(TRCD * DDR2CLKOUT/1000.0 - 1);
ddr2tim1.T_RP = ceil(TRP * DDR2CLKOUT/1000.0 - 1);
ddr2tim1.T_RFC = ceil(TRFC * DDR2CLKOUT/1000.0 - 1);
*SDTIM1 = *((int*)(&ddr2tim1));

ddr2tim2.T_CKE = TCKE - 1;
ddr2tim2.T_RTP = ceil(TRTP * DDR2CLKOUT/1000.0 - 1);;
ddr2tim2.T_XSRD = TXSRD - 1;
ddr2tim2.T_XSNR = ceil(TXSNR * DDR2CLKOUT/1000.0 - 1);
ddr2tim2.T_ODT = TODT;
*SDTIM2 = *((int*)(&ddr2tim2));

ddr2ctl.RL = ddr2cfg.CL + 1;
ddr2ctl.DDRPVTCNTL = 1;
ddr2ctl.DDRSLRATE = 1;
*DMCCTL = *((int*)(&ddr2ctl));

ddr2rfc.REFRESH_RATE = ceil(DDR2CLKOUT*REFRESHRATE);
ddr2rfc.SR = 0;
*SDRFC = *((int*)(&ddr2rfc));

ddr2cfg.BOOT_UNLOCK = 0; // LOCK
*SDCFG = *((int*)(&ddr2cfg));
ddr2cfg.TIMUNLOCK = 0; // LOCK
*SDCFG = *((int*)(&ddr2cfg));

 

*((int*)(0xE0000000)) = 0x01234567;

p = *((int*)(0xE0000000));      // Result pp = 0xffffffff

 

 

With correctly I configure?

 

  • 0
    TI__Guru* 84110 points

    Vladimir,

    I could not find a document sprugk5c on the TI website.

    Do you have one of our EVMs to compare with, or is this configuration of memory devices different than on our EVM?

    Is this a new board design of yours?

    What do you see on the pins when the write or read occurs?

    Did you start from known working DDR initialization code to get to the code above?

    It is not easy to tell from 150+ lines of code what might be wrong with your system. Do you have any additional methods to debug the code and the board?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 550 points

    >> I could not find a document sprugk5c on the TI website.
    http://www.ti.com/litv/pdf/sprugk5c

    >>Do you have one of our EVMs to compare with, or is this configuration of memory devices different than on our EVM?

    Is this a new board design of yours?

    Yes. It is our board

    >> What do you see on the pins when the write or read occurs?



    >>Did you start from known working DDR initialization code to get to the code above?

     >>It is not easy to tell from 150+ lines of code what might be wrong with your system. Do you have any additional methods to debug the code and the board?

    I read sequence of initialization.
    Therefore also wanted to ask, whether correct at me sequence of record in operating registers.

     

    There is any example of a code by initialization DDR2 for 6457 ???

     

  • 0 in reply to Vladimir Solodky
    TI__Guru* 84110 points

    Vladimir Solodky said:
    >> I could not find a document sprugk5c on the TI website.
    http://www.ti.com/litv/pdf/sprugk5c

    This is unusual that it has been difficult for me to reach this document. I did finally find it with the URL www.ti.com/lit/sprugk5, but not with the one you listed, which should also have worked. I will make a note of this for further study.

    RandyP said:
    >>Do you have one of our EVMs to compare with

    If not, it would be good to acquire an EVM. There are many hardware problems you can have with a new board, and having a known good board is very helpful.

    Vladimir Solodky said:
    There is any example of a code by initialization DDR2 for 6457 ???

    The GEL scripts that come with the EVM perform the initialization of the DDR2 on the board. I do not have that board and do not have that file.

    For the available support files, please go to the TMS320C6457 Product Folder, click on Software and Tools, and look through the list of packages available. The MCSDK may be you best choice, but I have not tried it yet. The Chip Support Library for C6457 is also a good choice, and it usually has example files for running various operations with peripherals.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • 0 in reply to RandyP
    Intellectual 550 points

    We have made a mistake in payment distributing.
    Have simply closed DDRRCVIN - DDRRCVOUT signals and haven't sustained a condition of length described in spraag6d.pdf.
    http://www.ti.com/litv/pdf/spraag6d page 13.

    Can not work because of it DDR2?

  • 0 in reply to Vladimir Solodky
    TI__Guru* 84110 points

    The routing guidelines and device selection are critical to the operation of the DSP with DDR2 memory. These points you have found on your board must be changed to match the guidelines.

    You did a great job finding this discrepancy. Please keep us posted on your progress.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 550 points

    On what signals DDRRCVIN - DDRRCVOUT influence?

     

    Whether it is possible as that to force to work memory?

  • 0 in reply to Vladimir Solodky
    TI__Guru* 84110 points

    The DDR2 interface is a JEDEC standard to which we have designed this DSP's interface. There is a lot of publicly available literature about the signalling and technology.

    TI does not provide detailed design support for this interface. We have found that the best way for our customers to build reliable boards is for them to follow specific guidelines. We have performed simulations and silicon testing to confirm those guidelines.

    We do not have the support structure available to analyze or assist a non-conforming design. I apologize for any inconvenience this may cause for you.

    Regards,
    RandyP