Part Number: 66AK2G12
Hi,
I am trying to enable 25 MHz clock signal on H23 pin as MII reference clock for 2 Ethernet PHYs. The PHYs will be be driven by PRU0.
I have used the clock tree tool ver. 1.0.0.3 to evaluate the value to insert in proper registers. In this way I set the following registers:
BOOTCFG_ETHERNET_CLKCTL (0x02620698) = 0x6
BOOTCFG_ETHERNET_CFG (0x02620E20) = 0x0
BOOTCFG_NSS_PLL_CTL0 (0x02620358) = 0x7C083E42
When using k2g_evm board, I see with oscilloscope the proper clock waveforms (50 MHz with BOOTCFG_ETHERNET_CLKCTL = 0x4 and 25 MHz with BOOTCFG_ETHERNET_CLKCTL = 0x6) but with my custom board the H23 is fixed at 3V3.
I have set the H23 pin in mux-k2g.h as below
{ 136, MODE(1) } // CLKOUT pin
Consider that respect to k2g_evm board, I don't use the EMAC pins but 2 interfaces from PRU0 to obtain Ethernet ports. At this point one difference respect to k2g_evm is that mdio and netcp nodes are not listed in my dts file. See below my one
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree Source for K2G Industrial Communication Engine EVM
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "keystone-k2g.dtsi"
/ {
compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
model = "Texas Instruments K2G SoC - Hitachi Propulsion Controller (HPC) board";
chosen {
stdout-path = &uart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
&i2c2 {
status = "okay";
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
&keystone_usb0 {
status = "okay";
};
&usb0_phy {
status = "okay";
compatible = "nop-phy";
};
&usb0 {
dr_mode = "peripheral";
status = "okay";
};
&i2c1 {
status = "okay";
};
&qspi {
status = "okay";
flash0: m25p80@0 {
compatible = "s25fl512s","spi-flash","n25q512ax3";
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <96000000>;
#address-cells = <1>;
#size-cells = <1>;
cdns,tshsl-ns = <392>;
cdns,tsd2d-ns = <392>;
cdns,tchsh-ns = <100>;
cdns,tslch-ns = <100>;
block-size = <18>;
partition@0 {
label = "MLO";
reg = <0x00000000 0x00100000>;
};
partition@1 {
label = "u-boot.img";
reg = <0x00100000 0x00100000>;
};
partition@2 {
label = "fdt";
reg = <0x00200000 0x00040000>;
};
partition@3 {
label = "skern-k2g.bin";
reg = <0x00240000 0x00010000>;
};
partition@4 {
label = "ti-sci-firmware";
reg = <0x00250000 0x00010000>;
};
partition@5 {
label = "k2-fw-initrd.cpio.gz";
reg = <0x00260000 0x00020000>;
};
partition@6 {
label = "kernel";
reg = <0x00280000 0x00800000>;
};
partition@7 {
label = "file-system";
reg = <0x00A80000 0x03580000>;
};
};
};
&spi0 {
status = "okay";
spi0_nor: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <50000000>;
m25p,fast-read;
reg = <0>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x80000>;
read-only;
};
partition@1 {
label = "misc";
reg = <0x80000 0xf80000>;
};
};
};
&spi1 {
status = "okay";
spi1_nor: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <50000000>;
m25p,fast-read;
reg = <0>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x80000>;
read-only;
};
partition@1 {
label = "misc";
reg = <0x80000 0xf80000>;
};
};
};
Could be it the reason that don't allow to enable 25 MHz on H23 pin or there is an another explanation?
Regards
Graziano
