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AM6442: Clocking for two DP83867 architecture

Gunter Schmer
Genius 14422 points

Part Number: AM6442

Hi,

the EVM and SK show two DP83867 PHYs and the clocking architecture for it. 

Right now the 25MHz oscillator feeds into the LMK clock buffer and drives the CLKIN to the SOC, and also two clocks to the PHYs. This is option #1.

The DNI resistors disable an option #2 where a 25MHz crystal clocks the SOC, and CLKOUT drives the LMK clock buffer which then puts out two clocks to ethernet PHYs.

Is there any preference between those options?

Has the option #2 been proven?

Thanks!

--Gunter

  • 0
    TI__Guru 64665 points

    No. We have seen cases where some Ethernet PHYs are not able to function as expected if their clock has too much N-Cycle jitter. Therefore, the AM64x CLKOUT source option was not used as the default Ethernet PHY clock source. There is a plan to validate this option during bench characterization.

    Regards,
    Paul