• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 262 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AM6442: Is AM64x affected by any of the errata listed for AM65x or J721e?

AM6442: MCU+ SDK 07.03 sets DLFO which shouldn't be necessary

Dominic Rath
Mastermind 7540 points
Part Number: AM6442


Dear TI team,

while trying to analyze some performance issues with a FreeRTOS application running on an R5f core of an AM6442 I noticed that the DLFO bit in the auxiliary control register is set.

I tracked that to the code in source/kernel/nortos/dpl/r5/CacheP_armv7r.c that seems to unconditionally set the DLFO bit when CacheP_init() is executed.

According to the referenced thread, the AM64x shouldn't be affected by an AM65x errata for which DLFO was used as a workaround.

  • Is there a reason why DLFO is set unconditionally in the code?

Clearing that bit didn't anything about my current issue, but to avoid future issues I wanted to make sure I understand why DLFO is currently being set.

Regards,

Dominic

  • 0
    TI__Expert 8885 points

    Hi Dominic,

    Thanks for bringing this to our attention. Yes, you are correct that DLFO should not be set for AM64x. AM64x does not have the issue like AM65x for which DLFO was used as a workaround.

    I filed a bug against the software and this should be fixed in future releases. I am closing this thread as nothing else to update.


    Thanks