I have some questions on the GPMC interface of the AM389x device.
In my actual design, I will be using the GPMC in address/data multiplexed mode (synchronous) to interface with an FPGA. On the FPGA side, I have some concerns to find a way how to distinguish a single read access and a burst read access. Because of the read cycle wait states, a single read cycle will keep the OE signal low for a few clock cycles, same as for a burst access.
1. For incrementing burst accesses, does the address bits A[27..17] change while WE/OE are low and ADV is high ? In other words, does the GPMC increments the address in some kind of way of the address bus, or it puts only the starting address of the burst during ADV is low.
2. If ADV is kept low for more than one clock cycle (using ADVONTIME) during a burst access, will the address bus change (increment) ?
3. How does a NOR flash distinguish single and burst read accesses ? They probably have the same concern that I have in my FPGA...
Any input is appreciated.
