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6472 Ethernet Boot

Graeme Parker
Expert 1265 points


Hello

I have a Xilinx FPGA which is reading from flash memory in order to boot an attached 6472 via Ethernet.

The FPGA receives the boot announcement from the 6472 and this decodes correctly, but I'm not totally sure what EXACTLY the FPGA should respond with.

The test packet I have should just write to one memory location which I can check with Code Composer (CCS).

There's no high-level functions available from the FPGA, so the boot packet is simply constructed as follows:

0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xD5, // preamble

0x3C, 0x2D, 0xB7, 0x7C, 0x72, 0x98, // dest MAC - this is the MAC the FPGA receives from the boot announcement.

0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x08, 0x00, // src MAC, ipv4

0x45, 0x00, 0x00, 0x34, 0x00, 0x01, 0x00, 0x00, 0x10, 0x11, 0xAA, 0xB9, // ipv4, len 0034, id, ttl, protocol, chksum - I'm sure these bytes are ok.

0,0,0,0, 0,0,0,0, // src ip, dst ip

0x00, 0x43, 0x00, 0x44, 0x00, 0x20, 0x00, 0x00, // src port, dst port, len 0020, chksum - I'm not sure about the port numbers?

0x54, 0x4B, 0x01, // magic #, opcode

0x00, 0,0,0,0, 0,0,0,4, 0,0x80,0x80,0, 0x12,0x34,0x56,0x78, 0,0,0,0 - sequence 0, execution address 0, length 4, destination 0x00808000, data 0x12345678, 0 to terminate

Using CCS I can see the received packet is ok (it's stored at 0x00F00000) and the EMAC0 registers indicate that there is no CRC and a good rx frame. But the address 0x00808000 does not contain 0x12345678. Why is this?

If anyone has a simple boot packet I can test that'd also be a great start. Thanks.

  • 0
    TI__Genius 9915 points

    Graeme,

    You can get the sample code in boot test package available in the TI Wiki page. See the link below:

    http://processors.wiki.ti.com/index.php/C6472

    Thanks,

    Arun

     

  • 0 in reply to ArunMani
    Expert 1265 points

    Thanks.

    Is there any documentation that tells you what's in this package?

    If I try to use the BootPacket.exe in utilities, what's the format to enter my own MAC addresses? I'm assuming I have to use hex6x first to convert my .out file into a boot table: hex6x -boot -a -e _c_int00 -order L -memwidth 32 -romwidth 32 -o filename.hex filename.out?

    I see in EMACboot\output there is a simple.eth file. Is this a complete Ethernet header? It doesn't look like one to me!

     

  • 0 in reply to Graeme Parker
    Expert 1265 points

     Thanks. I now have EMAC booting working great. But we have two DSPs in this system; each with a separate EMAC connection to our FPGA.

    The problem I have just encountered is that I cannot boot DSP2 as there is a board design error and pin CFGGP4 is not connected. This has an IPD in the DSP and therefor the PLL1 will be working at x10 and not x20. I don't know if it should still work at x10 (it doesn't send an un-interrupted Ethernet Acknowledge packet). Is there a required relationship between PLL1 (core clock) and PLL2 (EMAC clock)? That is, does PLL1 need to be as fast as (or faster) than PLL2?

    We also have I2C connections from the FPGA to each DSP. So, if we set the boot mode to I2C slave (is this an option for the 6472; it's mentioned in the datasheet but not in spruec6e?), then alter the PLL1 Multiplier during I2C boot, and then continue with an EMAC boot? Simply put and following the normal boot table format, the I2C boot would first send the execution address (of the EMAC boot entry point), then a length of 1 word, then the address of the PLL1 multiplier register, then a single word for the PLL1 multiplier register (13h), then a termination record of 0.

     

  • 0 in reply to Graeme Parker
    TI__Genius 9915 points

    I2C slave boot is supported.. It is explained in the bootloader UG. Check the c6472 product page.

     

    Thanks,

    Arun.

  • 0 in reply to ArunMani
    Expert 1265 points

    I am looking at spruec6f section 4.3, which is the C6472 boot mode options. Section 4.3.3 details I2C EEPROM boot mode, there is no slave boot description.

    So I'll assume it's the same as the 6454/6455 I2C slave boot. Section 2.3.5 mentions that the default slave address is 0x0, but later it states 04 as the slave address in I2C boot mode. The slave address for the 6472 is 0x50/0x51.

    But my main question is can I perform a simple pre-boot using I2C (and JUST change the PLL1 multipler to 0x13), and then jump back into the DSP's bootloader at the EMAC boot point (without affecting PLL1)? Can you suggest if this is possible and where the entry point on the internal boot loader is for EMAC booting.

    Thanks again.