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Original question:

AM5728: U-boot-spl early crash in enable_caches()

DRA718: u-boot crash observed when enable_caches() is enabled on TIDEP-0097

Premkiran Mannava
Prodigy 70 points
Part Number: DRA718
Other Parts Discussed in Thread: TIDEP-0097, , DRA742

Hi TI Team, 

We are doing u-boot bringup of DRA718 based TIDEP-0097 design, where we are using Processor SDK for Linux version 6_00_00_03. After board_init_r is triggered, in the enable_caches() function, the u-boot SPL code is observed to crash. Following the following link,  

we tried to disable the same in the SPL, but we are unable to proceed as the dts / dtb file associated is not getting parsed, we have used the same DTB file simillar to that of EVM. 
We would like to know if you have any suggestions on the same, to look at so that we would overcome this issue. The same u-boot SPL, is running fine on the DRA7XX EVM board, which has DRA742 processor.
Request your suggestions here. 
  • 0
    TI__Guru*** 147100 points

    Hi,

    Few questions:

    1) Are you using dra7xx_evm_defconfig for your custom board as well for building u-boot?
    2) What are the DTB changes done for your custom board?

    Best Regards,
    Keerthy

  • 0 in reply to Keerthy J
    Prodigy 70 points

    Hi,

    We have used dra7xx_evm_defconfig - same for our board which is same as TIDEP-0097 design. 

    We disabled caches as per your earlier reference post and tried, but having same issue. We have changed form UART1 to UART3, and the mux, as the current TIDEP-0097 design uses UART3 as debug UART. 

    Also We have modified the mux accordingly. 

    We are using the Microchip DDR3L - MT41K512M16  - 64 Meg 16 x 8 banks Twindie DDR3L, We are able to do stress test properly on this DDR3L using GEL file from 0x80000000 to 0xf00000E0. Last few locations are not manually writable. However, the DTB parse fails in the current scenario. 

  • 0 in reply to Premkiran Mannava
    TI__Guru*** 147100 points

    Hi,

    Please share the logs on where exactly it is failing. I need more details to analyze. What is the total DDR capacity?

    Best Regards,
    Keerthy