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Original question:

[K2H, MCSDK, 10GigE] 10 GigE performance and recipes to use RTM-BOC with K2H EVM

66AK2H14: IEEE1588 how to adjust frequency

zzMcGee T
Prodigy 60 points
Part Number: 66AK2H14


I'm using XTCIEVMK2X ver4.0 board and trying to do some experiments with PTP. I have PTPd successfully using my device driver that implements hardware time stamping (with CPTS module). Some functionality that I'm missing is adjust frequency capability. In a Keystone 2 "Time Synchronization" power point, there's mention that I should be able to do this by writing to DAC over SPI. I was hoping for more information about this (I'm not seeing anything about VCX0, DAC, or SPI in Keystone PLL user's guide). Also is there anywhere I could get reference driver and/or DPLL SW that's alluded to in that power point?

  • 0
    Prodigy 60 points

    From schematic I see the following from SPI getting fed to DAC->VCTCXO which I'm guessing is what the power point was referring to:

    I'm still a bit confused as to what addresses, registers, etc. to do what I'd like. Right now I'm using the default RFTCLK set to SYSCLK2 so any help on how to appropriately adjust the frequency would be greatly appreciated.

    I'd like to note that the end of this thread (CPTS PPS (Pulse-Per-Secon) using gigabit ethernet on evmk2h - Processors forum - Processors - TI E2E support forums) appears to be asking the same question I'm asking here but it unfortunately didn't get resolved.

    In a similar vein, from the Processor SDK Linux documentation (3.3.4. Kernel Drivers — Processor SDK Linux Documentation), I stumbled on this note:

    Note 5: (WARNING) On Keystone 2 platforms, the default rftclk select is the internal SYSCLK2. On K2L, core pll is configured (based on the programmed efuse of max speed of 1 GHz and ref clk of 122880000 Hz) to 1000594244 Hz. As such, SYSCLK2 = 1000594244 / 2 = 500297122 Hz. With such a rftclk frequency, it is unlikely that some “good” M/S/D can be found so that 1000000000 = ((500297122 * M) >> S) / D. Hence based on the algorithm in Note 4, the M/S/D corresponding to 500000000 Hz will be used and unfortunately inaccuracy will be observed in timestamping. However, this issue is not observed on K2HK and K2E since the respective core pll is configured to exactly 1200000000 Hz and 1000000000 Hz, thus the cpts rftclk frequency is 600000000 and 500000000 Hz respectively and “good” M/S/D exist for these rftclk frequencies.

    where are those frequency numbers coming from (so that I can determine them for myself)?

    Thanks

  • 0 in reply to zzMcGee T
    Prodigy 60 points

    For reference to what I'm trying to ultimately resolve. I'm running VxWorks and I've modified netcp device driver so that it works with a ported version of PTPd. The results look promising except for the observed drift:

    Right now when ptpd servo adjusts the frequency, I'm modifying a scale factor in software that's used for translating the cycle count to nanoseconds and not actually changing the hardware clock frequency since the observed drift is stable but relatively high.