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clock issues when using EMIF

Chongding Zhao
Prodigy 110 points

Hi

Got a question here regarding clock/emif issues for VC5505. We noticed that on our demo board the dsp clock (even crystal output) becomes unstable when we try to using EMIF to access external memory.  The unstable clock screws up both jtag and dsp.  Then we did two more sets of tests to check what causes the failure. 

1) Still using 32.768kHz crystal to generate dsp clock. But try different clock rates at 12.28M, 60M, and 100MHz. No luck for either of them. Clock becomes unstable even when trying to access the non-existent external memory

2) Use 10MHz external clock (from signal generator)  to generate dsp clock. Still try above dsp clock rates. Clock becomes less unstable compared to test 1). Only jtag is screwed up, but the dsp is able to access the memory

3) Try to run our project on VC5505 usbstick to verify the codes. Both clock and jtag/dsp are quite stable. 

After the tests, we guess the root cause may relate to crystal (e.g. board design or component selection). But we don't understand why accessing external memory could have such a big impact on clock? Without using EMIF, our demo board is quite stable. 

Anyone could shed some lights on this issue? Thanks very much!

 

Chuck

  • 0
    TI__Mastermind 23785 points

    Are the two load capacitors using RTC ground pin (VSSRTC)? Are they close to the DSP?

    Yes, it could be the quality of the crystal. Also, usually there is specification for the crystal's load capacitance. The load capacitors usually twice that value.

    Reference to the eZDSP schematic is another option.

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 110 points

    Hi Steve,

    The two load capacitors are grounded by connecting to RTC_VSS. Because load capacitance of our crystal is 12uF, we use 22uF capacitors. Only difference from eZDSP is we use two pin crystal while 4 pin crystal is used for eZDSP. After some study, we figure out the additional 2 pins of such crystal are dummy pins and could be floating or grounded. Moreover, both crystal and load capacitors are less than 8mm from DSP.

    We also found that both clock and external memory works fine when we fix memory location and  the data value. Failures happens only when we toggle address/data bus every access. We doubt if EMIF draw a lot current when address/data bus are toggling and, thus, introduce some interference to crystal circuits(because of some issues in our board design).  How much current EMIF typically draw? Potentially, could abnormal EMIF current affect clock/PLL circuits somewhat?

     

    Thanks

    Chongding