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TMS320DM8147 Bus

David Roberts
Prodigy 100 points
Other Parts Discussed in Thread: TMS320DM8147

Sorry for asking this question in the wrong Forum, but I didn't find one closer to my topic. I am a Newbie to TI bus cycles and this forum.

Various timing diagrams are given in the sprs647.pdf manual for the TMS320DM8147. I interface to an FPGA, therefore I can choose the optimum bus transfer type and then tailor the firmware to fit the bus cycle timing. Figures 8-xx describe timing for various GPMC read and write operations. I want to know which type of bus operation (multiplexed, non-multiplexed, asynchronous, synchronous), corresponding to which 8-xx figure number, achieves the highest throughput; whatever type of bus cycle that I choose, the same timing diagram must apply to CPU and DMA initiated bus cycles.

 

  • 0
    TI__Mastermind 43875 points

    David,

    If you look at each figure it is annotated with the particular mode that the diagram corresponds to.

    E.g. Figure 8-19 is annotated "GPMC Non-Multiplexed NOR Flash - Synchronous Single Read"

    The fact that it is targeted to NOR Flash is not really critical. The timing remains the same.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 100 points

    I accept what you say, Steve, but which type has the highest throughput in a CPU or DMA initiated bus cycle?  I can choose any type of transaction because I can program our FPGA accordingly.

    Is the type of transaction chosen in the GPMC setup for the particular chip select used?

    - David.

  • 0 in reply to David Roberts
    TI__Mastermind 43875 points

    David,

    Synchronous burst will have the best performance.

    DMA will give the best performance.

    I will need to check on the CS configuration, but it should be possible to re-configure this on the fly even if it is not automatic on a per CS basis.

    BR,

    Steve